return ['Disabled', 'Enabled'][v]
def output_power(v):
- return '%+ddBm' % [-4, -1, 2, 5][v]
+ return '{:+d}dBm'.format([-4, -1, 2, 5][v])
+# Notes on the implementation:
+# - Bit fields' width in registers determines the range of indices in
+# table/tuple lookups. Keep the implementation as robust as possible
+# during future maintenance. Avoid Python runtime errors when adjusting
+# the decoder.
regs = {
# reg: name offset width parser
0: [
('PD Polarity', 6, 1, lambda v: ['Negative', 'Positive'][v]),
('LDP', 7, 1, lambda v: ['10ns', '6ns'][v]),
('LDF', 8, 1, lambda v: ['FRAC-N', 'INT-N'][v]),
- ('Charge Pump Current Setting', 9, 4, lambda v: '%0.2fmA @ 5.1kΩ' %
- [0.31, 0.63, 0.94, 1.25, 1.56, 1.88, 2.19, 2.50,
- 2.81, 3.13, 3.44, 3.75, 4.06, 4.38, 4.69, 5.00][v]),
+ ('Charge Pump Current Setting', 9, 4, lambda v: '{curr:0.2f}mA @ 5.1kΩ'.format(
+ curr = (
+ 0.31, 0.63, 0.94, 1.25, 1.56, 1.88, 2.19, 2.50,
+ 2.81, 3.13, 3.44, 3.75, 4.06, 4.38, 4.69, 5.00,
+ )[v])),
('Double Buffer', 13, 1, disabled_enabled),
('R Counter', 14, 10, None),
('RDIV2', 24, 1, disabled_enabled),
('Reference Doubler', 25, 1, disabled_enabled),
- ('MUXOUT', 26, 3, lambda v:
- ['Three-State Output', 'DVdd', 'DGND', 'R Counter Output', 'N Divider Output',
- 'Analog Lock Detect', 'Digital Lock Detect', 'Reserved'][v]),
- ('Low Noise and Low Spur Modes', 29, 2, lambda v:
- ['Low Noise Mode', 'Reserved', 'Reserved', 'Low Spur Mode'][v])
+ ('MUXOUT', 26, 3, lambda v: '{text}'.format(
+ text = (
+ 'Three-State Output', 'DVdd', 'DGND',
+ 'R Counter Output', 'N Divider Output',
+ 'Analog Lock Detect', 'Digital Lock Detect',
+ 'Reserved'
+ )[v])),
+ ('Low Noise and Low Spur Modes', 29, 2, lambda v: '{text}'.format(
+ text = (
+ 'Low Noise Mode', 'Reserved', 'Reserved', 'Low Spur Mode'
+ )[v])),
],
3: [
('Clock Divider', 3, 12, None),
- ('Clock Divider Mode', 15, 2, lambda v:
- ['Clock Divider Off', 'Fast Lock Enable', 'Resync Enable', 'Reserved'][v]),
+ ('Clock Divider Mode', 15, 2, lambda v: '{text}'.format(
+ text = (
+ 'Clock Divider Off', 'Fast Lock Enable', 'Resync Enable', 'Reserved'
+ )[v])),
('CSR Enable', 18, 1, disabled_enabled),
('Charge Cancellation', 21, 1, disabled_enabled),
('ABP', 22, 1, lambda v: ['6ns (FRAC-N)', '3ns (INT-N)'][v]),
('AUX Output Enable', 9, 1, disabled_enabled),
('MTLD', 10, 1, disabled_enabled),
('VCO Power-Down', 11, 1, lambda v:
- 'VCO Powered ' + ('Down' if v == 1 else 'Up')),
+ 'VCO Powered {updown}'.format(updown = 'Down' if v else 'Up')),
('Band Select Clock Divider', 12, 8, None),
- ('RF Divider Select', 20, 3, lambda v: '÷' + str(2**v)),
+ ('RF Divider Select', 20, 3, lambda v: '÷{:d}'.format(2 ** v)),
('Feedback Select', 23, 1, lambda v: ['Divided', 'Fundamental'][v]),
],
5: [
- ('LD Pin Mode', 22, 2, lambda v:
- ['Low', 'Digital Lock Detect', 'Low', 'High'][v])
+ ('LD Pin Mode', 22, 2, lambda v: '{text}'.format(
+ text = (
+ 'Low', 'Digital Lock Detect', 'Low', 'High',
+ )[v])),
]
}
self.put(ss, es, self.out_ann, [ cls, data, ])
def decode_bits(self, offset, width):
+ '''Extract a bit field. Expects LSB input data.'''
bits = self.bits[offset:][:width]
ss, es = bits[-1][1], bits[0][2]
value = bitpack_lsb(bits, 0)
return ( value, ( ss, es, ))
def decode_field(self, name, offset, width, parser):
+ '''Interpret a bit field. Emits an annotation.'''
val, ( ss, es, ) = self.decode_bits(offset, width)
- val = parser(val) if parser else str(val)
- text = ['%s: %s' % (name, val)]
+ val = parser(val) if parser else '{}'.format(val)
+ text = ['{name}: {val}'.format(name = name, val = val)]
self.putg(ss, es, ANN_REG, text)
- return val
+
+ def decode_word(self, ss, es, bits):
+ '''Interpret a 32bit word after accumulation completes.'''
+ # SPI transfer content must be exactly one 32bit word.
+ count = len(self.bits)
+ if count != 32:
+ text = [
+ 'Frame error: Bit count: want 32, got {}'.format(count),
+ 'Frame error: Bit count',
+ 'Frame error',
+ ]
+ self.putg(ss, es, ANN_WARN, text)
+ return
+ # Holding bits in LSB order during interpretation simplifies
+ # bit field extraction. And annotation emitting routines expect
+ # this reverse order of bits' timestamps.
+ self.bits.reverse()
+ # Determine which register was accessed.
+ reg_addr, ( reg_ss, reg_es, ) = self.decode_bits(0, 3)
+ text = [
+ 'Register: {addr}'.format(addr = reg_addr),
+ 'Reg: {addr}'.format(addr = reg_addr),
+ '[{addr}]'.format(addr = reg_addr),
+ ]
+ self.putg(reg_ss, reg_es, ANN_REG, text)
+ # Interpret the register's content (when parsers are available).
+ field_descs = regs.get(reg_addr, None)
+ if not field_descs:
+ return
+ for field_desc in field_descs:
+ self.decode_field(*field_desc)
def decode(self, ss, es, data):
ptype, _, _ = data
if ptype == 'TRANSFER':
- if len(self.bits) == 32:
- self.bits.reverse()
- reg_value, ( reg_ss, reg_es, ) = self.decode_bits(0, 3)
- text = [
- 'Register: %d' % reg_value,
- 'Reg: %d' % reg_value,
- '[%d]' % reg_value,
- ]
- self.putg(reg_ss, reg_es, ANN_REG, text)
- if reg_value < len(regs):
- field_descs = regs[reg_value]
- for field_desc in field_descs:
- field = self.decode_field(*field_desc)
- else:
- text = [
- 'Frame error: Bit count: want 32, got %d' % len(self.bits),
- 'Frame error: Bit count',
- 'Frame error',
- ]
- self.putg(ss, es, ANN_WARN, text)
+ # Process accumulated bits after completion of a transfer.
+ self.decode_word(ss, es, self.bits)
self.bits.clear()
if ptype == 'BITS':
_, mosi_bits, miso_bits = data
- # Cope with the lower layer SPI decoder's output convention:
- # Regardless of wire transfer's frame format, .decode() input
- # provides BITS in the LE order. Accumulate in MSB order here,
- # and reverse before data processing when 'TRANSFER' is seen.
- mosi_bits = mosi_bits.copy()
- mosi_bits.reverse()
- self.bits.extend(mosi_bits)
+ # Accumulate bits in MSB order as they are seen in SPI frames.
+ msb_bits = mosi_bits.copy()
+ msb_bits.reverse()
+ self.bits.extend(msb_bits)
projects / libsigrokdecode.git / blobdiff