# Input modules
libsigrok_la_SOURCES += \
+ src/input/input.c \
src/input/binary.c \
src/input/chronovu_la8.c \
src/input/csv.c \
- src/input/input.c \
src/input/vcd.c \
src/input/wav.c
src/hardware/openbench-logic-sniffer/protocol.c \
src/hardware/openbench-logic-sniffer/api.c
endif
+if HW_PIPISTRELLO_OLS
+libsigrok_la_SOURCES += \
+ src/hardware/pipistrello-ols/protocol.h \
+ src/hardware/pipistrello-ols/protocol.c \
+ src/hardware/pipistrello-ols/api.c
+endif
if HW_RIGOL_DS
libsigrok_la_SOURCES += \
src/hardware/rigol-ds/protocol.h \
$(AM_V_GEN)python $< java $(CPPXMLDOC) > $@
$(JCXX): $(JSWG) $(JDOC) bindings/swig/classes.i $(library_include_HEADERS)
+ $(AM_V_at)make java-clean
$(AM_V_GEN)swig -c++ -java -package org.sigrok.core.classes \
-I$(srcdir)/include -I$(srcdir)/bindings/cxx/include -I$(srcdir) -I$(JCLS) -Ibindings/cxx/include -outdir $(JCLS) -o $@ $<