- /** The samplerate selected by the user. */
- uint64_t samplerate;
-
- /** The maximum sampling duration, in milliseconds. */
- uint64_t limit_msec;
-
- /** The maximum number of samples to acquire. */
- uint64_t limit_samples;
-
- /** Channels to use. */
- uint64_t channel_mask;
-
- uint64_t trigger_mask;
- uint64_t trigger_edge_mask;
- uint64_t trigger_values;
-
- struct acquisition_state *acquisition;
-
- struct regval_pair reg_write_seq[MAX_REG_WRITE_SEQ_LEN];
- int reg_write_pos;
- int reg_write_len;
-
- enum device_state state;
+ uint64_t samplerate; /* requested samplerate */
+ uint64_t limit_msec; /* requested capture duration in ms */
+ uint64_t limit_samples; /* requested capture length in samples */
+
+ uint64_t channel_mask; /* bit mask of enabled channels */
+ uint64_t trigger_mask; /* trigger enable mask */
+ uint64_t trigger_edge_mask; /* trigger type mask */
+ uint64_t trigger_values; /* trigger level/slope bits */
+
+ const struct model_info *model; /* device model descriptor */
+ struct acquisition_state *acquisition; /* running capture state */
+ int active_fpga_config; /* FPGA configuration index */
+ gboolean short_transfer_quirk; /* 64 bytes response limit */
+
+ enum protocol_state state; /* async protocol state */
+ gboolean cancel_requested; /* stop after current transfer */
+ gboolean transfer_error; /* error during device communication */
+
+ gboolean cfg_rle; /* RLE compression setting */
+ enum clock_source cfg_clock_source; /* clock source setting */
+ enum signal_edge cfg_clock_edge; /* ext clock edge setting */
+ enum trigger_source cfg_trigger_source; /* trigger source setting */
+ enum signal_edge cfg_trigger_slope; /* ext trigger slope setting */
+};