+ { SCPI_CMD_GET_OVER_CURRENT_PROTECTION_ENABLED, ":CURR:PROT:STAT?" },
+ { SCPI_CMD_SET_OVER_CURRENT_PROTECTION_ENABLE, ":CURR:PROT:STAT 1" },
+ { SCPI_CMD_SET_OVER_CURRENT_PROTECTION_DISABLE, ":CURR:PROT:STAT 0" },
+ { SCPI_CMD_GET_OVER_CURRENT_PROTECTION_ACTIVE, "STAT:QUES:COND?" },
+ { SCPI_CMD_GET_OVER_VOLTAGE_PROTECTION_ACTIVE, "STAT:QUES:COND?" },
+ { SCPI_CMD_GET_OVER_VOLTAGE_PROTECTION_THRESHOLD, ":VOLT:PROT?" },
+ { SCPI_CMD_SET_OVER_VOLTAGE_PROTECTION_THRESHOLD, ":VOLT:PROT %.6f" },
+ { SCPI_CMD_GET_OVER_TEMPERATURE_PROTECTION_ACTIVE, "STAT:QUES:COND?" },
+ { SCPI_CMD_GET_OUTPUT_REGULATION, "STAT:OPER:COND?" },
+ ALL_ZERO
+};
+
+static int hp_6630b_init_acquisition(const struct sr_dev_inst *sdi)
+{
+ struct sr_scpi_dev_inst *scpi;
+ int ret;
+
+ scpi = sdi->conn;
+
+ /*
+ * Monitor CV (256), CC+ (1024) and CC- (2048) bits of the
+ * Operational Status Register.
+ * Use both positive and negative transitions of the status bits.
+ */
+ ret = sr_scpi_send(scpi, "STAT:OPER:PTR 3328;NTR 3328;ENAB 3328");
+ if (ret != SR_OK)
+ return ret;
+
+ /*
+ * Monitor OVP (1), OCP (2), OTP (16) and Unreg (1024) bits of the
+ * Questionable Status Register.
+ * Use both positive and negative transitions of the status bits.
+ */
+ ret = sr_scpi_send(scpi, "STAT:QUES:PTR 1043;NTR 1043;ENAB 1043");
+ if (ret != SR_OK)
+ return ret;
+
+ /*
+ * Service Request Enable Register set for Operational Status Register
+ * bits (128) and Questionable Status Register bits (8).
+ * This masks the Status Register generating a SRQ/RQS. Not implemented yet!
+ */
+ /*
+ ret = sr_scpi_send(scpi, "*SRE 136");
+ if (ret != SR_OK)
+ return ret;
+ */
+
+ return SR_OK;
+}
+
+static int hp_6630b_update_status(const struct sr_dev_inst *sdi)
+{
+ struct sr_scpi_dev_inst *scpi;
+ int ret;
+ int stb;
+ int ques_even, ques_cond;
+ int oper_even, oper_cond;
+ gboolean output_enabled;
+ gboolean unreg, cv, cc_pos, cc_neg;
+ gboolean regulation_changed;
+ char *regulation;
+
+ scpi = sdi->conn;
+
+ unreg = FALSE;
+ cv = FALSE;
+ cc_pos = FALSE;
+ cc_neg = FALSE;
+ regulation_changed = FALSE;
+
+ /*
+ * Use SPoll when SCPI uses GPIB as transport layer.
+ * SPoll is approx. twice as fast as a normal GPIB write + read would be!
+ */
+#ifdef HAVE_LIBGPIB
+ char spoll_buf;
+
+ if (scpi->transport == SCPI_TRANSPORT_LIBGPIB) {
+ ret = sr_scpi_gpib_spoll(scpi, &spoll_buf);
+ if (ret != SR_OK)
+ return ret;
+ stb = (uint8_t)spoll_buf;
+ }
+ else {
+#endif
+ ret = sr_scpi_get_int(scpi, "*STB?", &stb);
+ if (ret != SR_OK)
+ return ret;
+#ifdef HAVE_LIBGPIB
+ }
+#endif
+
+ /* Questionable status summary bit */
+ if (stb & (1 << 3)) {
+ /* Read the event register to clear it! */
+ ret = sr_scpi_get_int(scpi, "STAT:QUES:EVEN?", &ques_even);
+ if (ret != SR_OK)
+ return ret;
+ /* Now get the values. */
+ ret = sr_scpi_get_int(scpi, "STAT:QUES:COND?", &ques_cond);
+ if (ret != SR_OK)
+ return ret;
+
+ /* OVP */
+ if (ques_even & (1 << 0))
+ sr_session_send_meta(sdi, SR_CONF_OVER_VOLTAGE_PROTECTION_ACTIVE,
+ g_variant_new_boolean(ques_cond & (1 << 0)));
+
+ /* OCP */
+ if (ques_even & (1 << 1))
+ sr_session_send_meta(sdi, SR_CONF_OVER_CURRENT_PROTECTION_ACTIVE,
+ g_variant_new_boolean(ques_cond & (1 << 1)));
+
+ /* OTP */
+ if (ques_even & (1 << 4))
+ sr_session_send_meta(sdi, SR_CONF_OVER_TEMPERATURE_PROTECTION_ACTIVE,
+ g_variant_new_boolean(ques_cond & (1 << 4)));
+
+ /* UNREG */
+ unreg = (ques_cond & (1 << 10));
+ regulation_changed = (ques_even & (1 << 10)) | regulation_changed;
+
+ /*
+ * Check if output state has changed, due to one of the
+ * questionable states changed.
+ * NOTE: The output state is sent even if it hasn't changed,
+ * but that only happens rarely.
+ */
+ ret = sr_scpi_get_bool(scpi, "OUTP:STAT?", &output_enabled);
+ if (ret != SR_OK)
+ return ret;
+ sr_session_send_meta(sdi, SR_CONF_ENABLED,
+ g_variant_new_boolean(output_enabled));
+ }
+
+ /* Operation status summary bit */
+ if (stb & (1 << 7)) {
+ /* Read the event register to clear it! */
+ ret = sr_scpi_get_int(scpi, "STAT:OPER:EVEN?", &oper_even);
+ if (ret != SR_OK)
+ return ret;
+ /* Now get the values. */
+ ret = sr_scpi_get_int(scpi, "STAT:OPER:COND?", &oper_cond);
+ if (ret != SR_OK)
+ return ret;
+
+ /* CV */
+ cv = (oper_cond & (1 << 8));
+ regulation_changed = (oper_even & (1 << 8)) | regulation_changed;
+ /* CC+ */
+ cc_pos = (oper_cond & (1 << 10));
+ regulation_changed = (oper_even & (1 << 10)) | regulation_changed;
+ /* CC- */
+ cc_neg = (oper_cond & (1 << 11));
+ regulation_changed = (oper_even & (1 << 11)) | regulation_changed;
+ }
+
+ if (regulation_changed) {
+ if (cv && !cc_pos && !cc_neg && !unreg)
+ regulation = "CV";
+ else if (cc_pos && !cv && !cc_neg && !unreg)
+ regulation = "CC";
+ else if (cc_neg && !cv && !cc_pos && !unreg)
+ regulation = "CC-";
+ else if (unreg && !cv && !cc_pos && !cc_neg)
+ regulation = "UR";
+ else if (!cv && !cc_pos && !cc_neg && !unreg)
+ /* This happens in case of OCP active. */
+ regulation = "";
+ else {
+ /* This happens from time to time (CV and CC+ active). */
+ sr_dbg("Undefined regulation for HP 66xxB "
+ "(CV=%i, CC+=%i, CC-=%i, UR=%i).",
+ cv, cc_pos, cc_neg, unreg);
+ return FALSE;
+ }
+ sr_session_send_meta(sdi, SR_CONF_REGULATION,
+ g_variant_new_string(regulation));
+ }
+
+ return SR_OK;
+}
+
+/* Owon P4000 series */
+static const uint32_t owon_p4000_devopts[] = {
+ SR_CONF_CONTINUOUS,
+ SR_CONF_LIMIT_SAMPLES | SR_CONF_GET | SR_CONF_SET,
+ SR_CONF_LIMIT_MSEC | SR_CONF_GET | SR_CONF_SET
+};
+
+static const uint32_t owon_p4000_devopts_cg[] = {
+ SR_CONF_ENABLED | SR_CONF_GET | SR_CONF_SET,
+ SR_CONF_VOLTAGE | SR_CONF_GET,
+ SR_CONF_VOLTAGE_TARGET | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST,
+ SR_CONF_CURRENT | SR_CONF_GET,
+ SR_CONF_CURRENT_LIMIT | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST,
+ SR_CONF_OVER_VOLTAGE_PROTECTION_THRESHOLD | SR_CONF_GET | SR_CONF_SET,
+ SR_CONF_OVER_CURRENT_PROTECTION_THRESHOLD | SR_CONF_GET | SR_CONF_SET,
+};
+
+static const struct channel_spec owon_p4603_ch[] = {
+ { "1", { 0.01, 60, 0.001, 3, 3 }, { 0.001, 3, 0.001, 3, 3 }, { 0, 180, 0, 3, 3 }, FREQ_DC_ONLY, { 0.01, 61, 0.001}, { 0.001, 3.1, 0.001} },
+};
+
+static const struct channel_spec owon_p4305_ch[] = {
+ { "1", { 0.01, 30, 0.001, 3, 3 }, { 0.001, 5, 0.001, 3, 3 }, { 0, 180, 0, 3, 3 }, FREQ_DC_ONLY, { 0.01, 31, 0.001}, { 0.001, 3.1, 0.001} },
+};
+
+static const struct channel_group_spec owon_p4000_cg[] = {
+ { "1", CH_IDX(0), PPS_OVP | PPS_OCP, SR_MQFLAG_DC },
+};
+
+static const struct scpi_command owon_p4000_cmd[] = {
+ { SCPI_CMD_GET_MEAS_VOLTAGE, "MEAS:VOLT?" },
+ { SCPI_CMD_GET_MEAS_CURRENT, "MEAS:CURR?" },
+ { SCPI_CMD_GET_MEAS_POWER, "MEAS:POW?" },
+ { SCPI_CMD_GET_VOLTAGE_TARGET, "VOLT?" },
+ { SCPI_CMD_SET_VOLTAGE_TARGET, "VOLT %.6f" },
+ { SCPI_CMD_GET_CURRENT_LIMIT, "CURR?" },
+ { SCPI_CMD_SET_CURRENT_LIMIT, "CURR %.6f" },
+ { SCPI_CMD_GET_OUTPUT_ENABLED, "OUTP?" },
+ { SCPI_CMD_SET_OUTPUT_ENABLE, "OUTP 1" },
+ { SCPI_CMD_SET_OUTPUT_DISABLE, "OUTP 0" },
+ { SCPI_CMD_GET_OVER_VOLTAGE_PROTECTION_THRESHOLD, "VOLT:LIM?" },
+ { SCPI_CMD_SET_OVER_VOLTAGE_PROTECTION_THRESHOLD, "VOLT:LIM %.6f" },
+ { SCPI_CMD_GET_OVER_CURRENT_PROTECTION_THRESHOLD, "CURR:LIM?" },
+ { SCPI_CMD_SET_OVER_CURRENT_PROTECTION_THRESHOLD, "CURR:LIM %.6f" },
+ ALL_ZERO
+};
+
+/* Philips/Fluke PM2800 series */
+static const uint32_t philips_pm2800_devopts[] = {
+ SR_CONF_CONTINUOUS,
+ SR_CONF_LIMIT_SAMPLES | SR_CONF_GET | SR_CONF_SET,
+ SR_CONF_LIMIT_MSEC | SR_CONF_GET | SR_CONF_SET,
+};
+
+static const uint32_t philips_pm2800_devopts_cg[] = {
+ SR_CONF_ENABLED | SR_CONF_GET | SR_CONF_SET,
+ SR_CONF_VOLTAGE | SR_CONF_GET,
+ SR_CONF_VOLTAGE_TARGET | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST,
+ SR_CONF_CURRENT | SR_CONF_GET,
+ SR_CONF_CURRENT_LIMIT | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST,
+ SR_CONF_OVER_VOLTAGE_PROTECTION_ACTIVE | SR_CONF_GET,
+ SR_CONF_OVER_VOLTAGE_PROTECTION_THRESHOLD | SR_CONF_GET | SR_CONF_SET,
+ SR_CONF_OVER_CURRENT_PROTECTION_ENABLED | SR_CONF_GET | SR_CONF_SET,
+ SR_CONF_OVER_CURRENT_PROTECTION_ACTIVE | SR_CONF_GET,
+ SR_CONF_REGULATION | SR_CONF_GET,
+};
+
+enum philips_pm2800_modules {
+ PM2800_MOD_30V_10A = 1,
+ PM2800_MOD_60V_5A,
+ PM2800_MOD_60V_10A,
+ PM2800_MOD_8V_15A,
+ PM2800_MOD_60V_2A,
+ PM2800_MOD_120V_1A,
+};
+
+static const struct philips_pm2800_module_spec {
+ /* Min, max, programming resolution. */
+ double voltage[5];
+ double current[5];
+ double power[5];
+} philips_pm2800_module_specs[] = {
+ /* Autoranging modules. */
+ [PM2800_MOD_30V_10A] = { { 0, 30, 0.0075, 2, 4 }, { 0, 10, 0.0025, 2, 4 }, { 0, 60 } },
+ [PM2800_MOD_60V_5A] = { { 0, 60, 0.015, 2, 3 }, { 0, 5, 0.00125, 2, 5 }, { 0, 60 } },
+ [PM2800_MOD_60V_10A] = { { 0, 60, 0.015, 2, 3 }, { 0, 10, 0.0025, 2, 5 }, { 0, 120 } },
+ /* Linear modules. */
+ [PM2800_MOD_8V_15A] = { { 0, 8, 0.002, 3, 3 }, { -15, 15, 0.00375, 3, 5 }, { 0, 120 } },
+ [PM2800_MOD_60V_2A] = { { 0, 60, 0.015, 2, 3 }, { -2, 2, 0.0005, 3, 4 }, { 0, 120 } },
+ [PM2800_MOD_120V_1A] = { { 0, 120, 0.030, 2, 2 }, { -1, 1, 0.00025, 3, 5 }, { 0, 120 } },
+};
+
+static const struct philips_pm2800_model {
+ unsigned int chassis;
+ unsigned int num_modules;
+ unsigned int set;
+ unsigned int modules[3];
+} philips_pm2800_matrix[] = {
+ /* Autoranging chassis. */
+ { 1, 1, 0, { PM2800_MOD_30V_10A, 0, 0 } },
+ { 1, 1, 1, { PM2800_MOD_60V_5A, 0, 0 } },
+ { 1, 2, 0, { PM2800_MOD_30V_10A, PM2800_MOD_30V_10A, 0 } },
+ { 1, 2, 1, { PM2800_MOD_60V_5A, PM2800_MOD_60V_5A, 0 } },
+ { 1, 2, 2, { PM2800_MOD_30V_10A, PM2800_MOD_60V_5A, 0 } },
+ { 1, 2, 3, { PM2800_MOD_30V_10A, PM2800_MOD_60V_10A, 0 } },
+ { 1, 2, 4, { PM2800_MOD_60V_5A, PM2800_MOD_60V_10A, 0 } },
+ { 1, 3, 0, { PM2800_MOD_30V_10A, PM2800_MOD_30V_10A, PM2800_MOD_30V_10A } },
+ { 1, 3, 1, { PM2800_MOD_60V_5A, PM2800_MOD_60V_5A, PM2800_MOD_60V_5A } },
+ { 1, 3, 2, { PM2800_MOD_30V_10A, PM2800_MOD_30V_10A, PM2800_MOD_60V_5A } },
+ { 1, 3, 3, { PM2800_MOD_30V_10A, PM2800_MOD_60V_5A, PM2800_MOD_60V_5A } },
+ /* Linear chassis. */
+ { 3, 1, 0, { PM2800_MOD_60V_2A, 0, 0 } },
+ { 3, 1, 1, { PM2800_MOD_120V_1A, 0, 0 } },
+ { 3, 1, 2, { PM2800_MOD_8V_15A, 0, 0 } },
+ { 3, 2, 0, { PM2800_MOD_60V_2A, 0, 0 } },
+ { 3, 2, 1, { PM2800_MOD_120V_1A, 0, 0 } },
+ { 3, 2, 2, { PM2800_MOD_60V_2A, PM2800_MOD_120V_1A, 0 } },
+ { 3, 2, 3, { PM2800_MOD_8V_15A, PM2800_MOD_8V_15A, 0 } },
+};
+
+static const char *philips_pm2800_names[] = { "1", "2", "3" };
+
+static int philips_pm2800_probe_channels(struct sr_dev_inst *sdi,
+ struct sr_scpi_hw_info *hw_info,
+ struct channel_spec **channels, unsigned int *num_channels,
+ struct channel_group_spec **channel_groups, unsigned int *num_channel_groups)
+{
+ const struct philips_pm2800_model *model;
+ const struct philips_pm2800_module_spec *spec;
+ unsigned int chassis, num_modules, set, module, m, i;
+
+ (void)sdi;
+
+ /*
+ * The model number as reported by *IDN? looks like e.g. PM2813/11,
+ * Where "PM28" is fixed, followed by the chassis code (1 = autoranging,
+ * 3 = linear series) and the number of modules: 1-3 for autoranging,
+ * 1-2 for linear.
+ * After the slash, the first digit denotes the module set. The
+ * digit after that denotes front (5) or rear (1) binding posts.
+ */
+ chassis = hw_info->model[4] - 0x30;
+ num_modules = hw_info->model[5] - 0x30;
+ set = hw_info->model[7] - 0x30;
+ for (m = 0; m < ARRAY_SIZE(philips_pm2800_matrix); m++) {
+ model = &philips_pm2800_matrix[m];
+ if (model->chassis == chassis && model->num_modules == num_modules
+ && model->set == set)
+ break;
+ }
+ if (m == ARRAY_SIZE(philips_pm2800_matrix)) {
+ sr_dbg("Model %s not found in matrix.", hw_info->model);
+ return SR_ERR;
+ }
+
+ sr_dbg("Found %d output channel%s:", num_modules, num_modules > 1 ? "s" : "");
+ *channels = g_malloc0(sizeof(struct channel_spec) * num_modules);
+ *channel_groups = g_malloc0(sizeof(struct channel_group_spec) * num_modules);
+ for (i = 0; i < num_modules; i++) {
+ module = model->modules[i];
+ spec = &philips_pm2800_module_specs[module];
+ sr_dbg("output %d: %.0f - %.0fV, %.0f - %.0fA, %.0f - %.0fW", i + 1,
+ spec->voltage[0], spec->voltage[1],
+ spec->current[0], spec->current[1],
+ spec->power[0], spec->power[1]);
+ (*channels)[i].name = (char *)philips_pm2800_names[i];
+ memcpy(&((*channels)[i].voltage), spec, sizeof(double) * 15);
+ (*channel_groups)[i].name = (char *)philips_pm2800_names[i];
+ (*channel_groups)[i].channel_index_mask = 1 << i;
+ (*channel_groups)[i].features = PPS_OTP | PPS_OVP | PPS_OCP;
+ (*channel_groups)[i].mqflags = SR_MQFLAG_DC;
+ }
+ *num_channels = *num_channel_groups = num_modules;
+
+ return SR_OK;
+}
+
+static const struct scpi_command philips_pm2800_cmd[] = {
+ { SCPI_CMD_SELECT_CHANNEL, ":INST:NSEL %s" },
+ { SCPI_CMD_GET_MEAS_VOLTAGE, ":MEAS:VOLT?" },
+ { SCPI_CMD_GET_MEAS_CURRENT, ":MEAS:CURR?" },
+ { SCPI_CMD_GET_VOLTAGE_TARGET, ":SOUR:VOLT?" },
+ { SCPI_CMD_SET_VOLTAGE_TARGET, ":SOUR:VOLT %.6f" },
+ { SCPI_CMD_GET_CURRENT_LIMIT, ":SOUR:CURR?" },
+ { SCPI_CMD_SET_CURRENT_LIMIT, ":SOUR:CURR %.6f" },
+ { SCPI_CMD_GET_OUTPUT_ENABLED, ":OUTP?" },
+ { SCPI_CMD_SET_OUTPUT_ENABLE, ":OUTP ON" },
+ { SCPI_CMD_SET_OUTPUT_DISABLE, ":OUTP OFF" },
+ { SCPI_CMD_GET_OUTPUT_REGULATION, ":SOUR:FUNC:MODE?" },
+ { SCPI_CMD_GET_OVER_VOLTAGE_PROTECTION_ACTIVE, ":SOUR:VOLT:PROT:TRIP?" },
+ { SCPI_CMD_GET_OVER_VOLTAGE_PROTECTION_THRESHOLD, ":SOUR:VOLT:PROT:LEV?" },
+ { SCPI_CMD_SET_OVER_VOLTAGE_PROTECTION_THRESHOLD, ":SOUR:VOLT:PROT:LEV %.6f" },
+ { SCPI_CMD_GET_OVER_CURRENT_PROTECTION_ENABLED, ":SOUR:CURR:PROT:STAT?" },
+ { SCPI_CMD_SET_OVER_CURRENT_PROTECTION_ENABLE, ":SOUR:CURR:PROT:STAT ON" },
+ { SCPI_CMD_SET_OVER_CURRENT_PROTECTION_DISABLE, ":SOUR:CURR:PROT:STAT OFF" },
+ { SCPI_CMD_GET_OVER_CURRENT_PROTECTION_ACTIVE, ":SOUR:CURR:PROT:TRIP?" },
+ ALL_ZERO
+};
+
+static const uint32_t rs_hmc8043_devopts[] = {
+ SR_CONF_CONTINUOUS,
+ SR_CONF_LIMIT_SAMPLES | SR_CONF_GET | SR_CONF_SET,
+ SR_CONF_LIMIT_MSEC | SR_CONF_GET | SR_CONF_SET,
+};
+
+static const uint32_t rs_hmc8043_devopts_cg[] = {
+ SR_CONF_OVER_VOLTAGE_PROTECTION_ENABLED | SR_CONF_GET | SR_CONF_SET,
+ SR_CONF_OVER_VOLTAGE_PROTECTION_ACTIVE | SR_CONF_GET,
+ SR_CONF_OVER_VOLTAGE_PROTECTION_THRESHOLD | SR_CONF_GET | SR_CONF_SET,
+ SR_CONF_VOLTAGE | SR_CONF_GET,
+ SR_CONF_VOLTAGE_TARGET | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST,
+ SR_CONF_CURRENT | SR_CONF_GET,
+ SR_CONF_CURRENT_LIMIT | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST,
+ SR_CONF_ENABLED | SR_CONF_GET | SR_CONF_SET,
+};
+
+static const struct channel_spec rs_hmc8043_ch[] = {
+ { "1", { 0, 32.050, 0.001, 3, 4 }, { 0.001, 3, 0.001, 3, 4 }, { 0, 0, 0, 0, 4 }, FREQ_DC_ONLY, NO_OVP_LIMITS, NO_OCP_LIMITS },
+ { "2", { 0, 32.050, 0.001, 3, 4 }, { 0.001, 3, 0.001, 3, 4 }, { 0, 0, 0, 0, 4 }, FREQ_DC_ONLY, NO_OVP_LIMITS, NO_OCP_LIMITS },
+ { "3", { 0, 32.050, 0.001, 3, 4 }, { 0.001, 3, 0.001, 3, 4 }, { 0, 0, 0, 0, 4 }, FREQ_DC_ONLY, NO_OVP_LIMITS, NO_OCP_LIMITS },
+};
+
+static const struct channel_group_spec rs_hmc8043_cg[] = {
+ { "1", CH_IDX(0), PPS_OVP, SR_MQFLAG_DC },
+ { "2", CH_IDX(1), PPS_OVP, SR_MQFLAG_DC },
+ { "3", CH_IDX(2), PPS_OVP, SR_MQFLAG_DC },
+};
+
+static const struct scpi_command rs_hmc8043_cmd[] = {
+ { SCPI_CMD_SELECT_CHANNEL, "INST:NSEL %s" },
+ { SCPI_CMD_GET_MEAS_VOLTAGE, "MEAS:VOLT?" },
+ { SCPI_CMD_GET_MEAS_CURRENT, "MEAS:CURR?" },
+ { SCPI_CMD_GET_VOLTAGE_TARGET, "VOLT?" },
+ { SCPI_CMD_SET_VOLTAGE_TARGET, "VOLT %.6f" },
+ { SCPI_CMD_GET_CURRENT_LIMIT, "CURR?" },
+ { SCPI_CMD_SET_CURRENT_LIMIT, "CURR %.6f" },
+ { SCPI_CMD_GET_OUTPUT_ENABLED, "OUTP?" },
+ { SCPI_CMD_SET_OUTPUT_ENABLE, "OUTP ON" },
+ { SCPI_CMD_SET_OUTPUT_DISABLE, "OUTP OFF" },
+ { SCPI_CMD_GET_OVER_VOLTAGE_PROTECTION_ACTIVE, "VOLT:PROT:TRIP?" },
+ { SCPI_CMD_GET_OVER_VOLTAGE_PROTECTION_THRESHOLD, "VOLT:PROT:LEV?" },
+ { SCPI_CMD_SET_OVER_VOLTAGE_PROTECTION_THRESHOLD, "VOLT:PROT:LEV %.6f" },
+ { SCPI_CMD_GET_OVER_VOLTAGE_PROTECTION_ENABLED, "VOLT:PROT:STAT?" },
+ { SCPI_CMD_SET_OVER_VOLTAGE_PROTECTION_ENABLE, "VOLT:PROT:STAT ON" },
+ { SCPI_CMD_SET_OVER_VOLTAGE_PROTECTION_DISABLE, "VOLT:PROT:STAT OFF" },
+ ALL_ZERO
+};
+
+static const uint32_t rs_hmp4040_devopts[] = {
+ SR_CONF_CONTINUOUS,
+ SR_CONF_LIMIT_SAMPLES | SR_CONF_GET | SR_CONF_SET,
+ SR_CONF_LIMIT_MSEC | SR_CONF_GET | SR_CONF_SET,
+};
+
+static const uint32_t rs_hmp4040_devopts_cg[] = {
+ SR_CONF_OVER_VOLTAGE_PROTECTION_ENABLED | SR_CONF_GET,
+ SR_CONF_OVER_VOLTAGE_PROTECTION_ACTIVE | SR_CONF_GET,
+ SR_CONF_OVER_VOLTAGE_PROTECTION_THRESHOLD | SR_CONF_GET | SR_CONF_SET,
+ SR_CONF_VOLTAGE | SR_CONF_GET,
+ SR_CONF_VOLTAGE_TARGET | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST,
+ SR_CONF_CURRENT | SR_CONF_GET,
+ SR_CONF_CURRENT_LIMIT | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST,
+ SR_CONF_ENABLED | SR_CONF_GET | SR_CONF_SET,
+ SR_CONF_OVER_TEMPERATURE_PROTECTION_ACTIVE | SR_CONF_GET,
+ SR_CONF_REGULATION | SR_CONF_GET,
+};
+
+static const struct channel_spec rs_hmp2020_ch[] = {
+ { "1", { 0, 32.050, 0.001, 3, 4 }, { 0.001, 10.01, 0.0002, 3, 4 }, { 0, 0, 0, 0, 4 }, FREQ_DC_ONLY, NO_OVP_LIMITS, NO_OCP_LIMITS },
+ { "2", { 0, 32.050, 0.001, 3, 4 }, { 0.001, 5.01, 0.0001, 3, 4 }, { 0, 0, 0, 0, 4 }, FREQ_DC_ONLY, NO_OVP_LIMITS, NO_OCP_LIMITS },