+/* Register mappings for old and new bitstream versions */
+
+enum fpga_register_id {
+ FPGA_REGISTER_VERSION,
+ FPGA_REGISTER_STATUS_CONTROL,
+ FPGA_REGISTER_CHANNEL_SELECT_LOW,
+ FPGA_REGISTER_CHANNEL_SELECT_HIGH,
+ FPGA_REGISTER_SAMPLE_RATE_DIVISOR,
+ FPGA_REGISTER_LED_BRIGHTNESS,
+ FPGA_REGISTER_PRIMER_DATA1,
+ FPGA_REGISTER_PRIMER_CONTROL,
+ FPGA_REGISTER_MODE,
+ FPGA_REGISTER_PRIMER_DATA2,
+ FPGA_REGISTER_MAX = FPGA_REGISTER_PRIMER_DATA2
+};
+
+enum fpga_status_control_bit {
+ FPGA_STATUS_CONTROL_BIT_RUNNING,
+ FPGA_STATUS_CONTROL_BIT_UPDATE,
+ FPGA_STATUS_CONTROL_BIT_UNKNOWN1,
+ FPGA_STATUS_CONTROL_BIT_OVERFLOW,
+ FPGA_STATUS_CONTROL_BIT_UNKNOWN2,
+ FPGA_STATUS_CONTROL_BIT_MAX = FPGA_STATUS_CONTROL_BIT_UNKNOWN2
+};
+
+enum fpga_mode_bit {
+ FPGA_MODE_BIT_CLOCK,
+ FPGA_MODE_BIT_UNKNOWN1,
+ FPGA_MODE_BIT_UNKNOWN2,
+ FPGA_MODE_BIT_MAX = FPGA_MODE_BIT_UNKNOWN2
+};
+
+static const uint8_t fpga_register_map_old[FPGA_REGISTER_MAX + 1] = {
+ [FPGA_REGISTER_VERSION] = 0,
+ [FPGA_REGISTER_STATUS_CONTROL] = 1,
+ [FPGA_REGISTER_CHANNEL_SELECT_LOW] = 2,
+ [FPGA_REGISTER_CHANNEL_SELECT_HIGH] = 3,
+ [FPGA_REGISTER_SAMPLE_RATE_DIVISOR] = 4,
+ [FPGA_REGISTER_LED_BRIGHTNESS] = 5,
+ [FPGA_REGISTER_PRIMER_DATA1] = 6,
+ [FPGA_REGISTER_PRIMER_CONTROL] = 7,
+ [FPGA_REGISTER_MODE] = 10,
+ [FPGA_REGISTER_PRIMER_DATA2] = 12,
+};
+
+static const uint8_t fpga_register_map_new[FPGA_REGISTER_MAX + 1] = {
+ [FPGA_REGISTER_VERSION] = 7,
+ [FPGA_REGISTER_STATUS_CONTROL] = 15,
+ [FPGA_REGISTER_CHANNEL_SELECT_LOW] = 1,
+ [FPGA_REGISTER_CHANNEL_SELECT_HIGH] = 6,
+ [FPGA_REGISTER_SAMPLE_RATE_DIVISOR] = 11,
+ [FPGA_REGISTER_LED_BRIGHTNESS] = 5,
+ [FPGA_REGISTER_PRIMER_DATA1] = 14,
+ [FPGA_REGISTER_PRIMER_CONTROL] = 2,
+ [FPGA_REGISTER_MODE] = 4,
+ [FPGA_REGISTER_PRIMER_DATA2] = 3,
+};
+
+static const uint8_t fpga_status_control_bit_map_old[FPGA_STATUS_CONTROL_BIT_MAX + 1] = {
+ [FPGA_STATUS_CONTROL_BIT_RUNNING] = 0x01,
+ [FPGA_STATUS_CONTROL_BIT_UPDATE] = 0x02,
+ [FPGA_STATUS_CONTROL_BIT_UNKNOWN1] = 0x08,
+ [FPGA_STATUS_CONTROL_BIT_OVERFLOW] = 0x20,
+ [FPGA_STATUS_CONTROL_BIT_UNKNOWN2] = 0x40,
+};
+
+static const uint8_t fpga_status_control_bit_map_new[FPGA_STATUS_CONTROL_BIT_MAX + 1] = {
+ [FPGA_STATUS_CONTROL_BIT_RUNNING] = 0x20,
+ [FPGA_STATUS_CONTROL_BIT_UPDATE] = 0x08,
+ [FPGA_STATUS_CONTROL_BIT_UNKNOWN1] = 0x10,
+ [FPGA_STATUS_CONTROL_BIT_OVERFLOW] = 0x01,
+ [FPGA_STATUS_CONTROL_BIT_UNKNOWN2] = 0x04,
+};
+
+static const uint8_t fpga_mode_bit_map_old[FPGA_MODE_BIT_MAX + 1] = {
+ [FPGA_MODE_BIT_CLOCK] = 0x01,
+ [FPGA_MODE_BIT_UNKNOWN1] = 0x40,
+ [FPGA_MODE_BIT_UNKNOWN2] = 0x80,
+};
+
+static const uint8_t fpga_mode_bit_map_new[FPGA_MODE_BIT_MAX + 1] = {
+ [FPGA_MODE_BIT_CLOCK] = 0x04,
+ [FPGA_MODE_BIT_UNKNOWN1] = 0x80,
+ [FPGA_MODE_BIT_UNKNOWN2] = 0x01,
+};
+
+#define FPGA_REG(x) \
+ (devc->fpga_register_map[FPGA_REGISTER_ ## x])
+
+#define FPGA_STATUS_CONTROL(x) \
+ (devc->fpga_status_control_bit_map[FPGA_STATUS_CONTROL_BIT_ ## x])
+
+#define FPGA_MODE(x) \
+ (devc->fpga_mode_bit_map[FPGA_MODE_BIT_ ## x])
+