uint64_t limit_frames = devc->limit_frames;
if (devc->num_frames_segmented != 0 && devc->num_frames_segmented < limit_frames)
limit_frames = devc->num_frames_segmented;
uint64_t limit_frames = devc->limit_frames;
if (devc->num_frames_segmented != 0 && devc->num_frames_segmented < limit_frames)
limit_frames = devc->num_frames_segmented;
return SR_ERR;
devc->analog_frame_size = devc->model->series->live_samples;
devc->digital_frame_size = devc->model->series->live_samples;
rigol_ds_set_wait_event(devc, WAIT_TRIGGER);
} else {
if (devc->model->series->protocol == PROTOCOL_V3) {
return SR_ERR;
devc->analog_frame_size = devc->model->series->live_samples;
devc->digital_frame_size = devc->model->series->live_samples;
rigol_ds_set_wait_event(devc, WAIT_TRIGGER);
} else {
if (devc->model->series->protocol == PROTOCOL_V3) {
{
/* The DS4000 series does not have a fixed memory depth, it
* can be chosen from the menu and also varies with number
{
/* The DS4000 series does not have a fixed memory depth, it
* can be chosen from the menu and also varies with number
{
/* The DS1000Z series has a fixed memory depth which we
* need to divide correctly according to the number of
{
/* The DS1000Z series has a fixed memory depth which we
* need to divide correctly according to the number of
return SR_ERR;
rigol_ds_set_wait_event(devc, WAIT_STOP);
if (devc->data_source == DATA_SOURCE_SEGMENTED &&
return SR_ERR;
rigol_ds_set_wait_event(devc, WAIT_STOP);
if (devc->data_source == DATA_SOURCE_SEGMENTED &&
if (devc->model->series->protocol >= PROTOCOL_V3 &&
ch->type == SR_CHANNEL_ANALOG) {
/* Vertical increment. */
if (devc->model->series->protocol >= PROTOCOL_V3 &&
ch->type == SR_CHANNEL_ANALOG) {
/* Vertical increment. */
MIN(devc->num_channel_bytes + ACQ_BLOCK_SIZE,
devc->analog_frame_size)) != SR_OK)
return TRUE;
MIN(devc->num_channel_bytes + ACQ_BLOCK_SIZE,
devc->analog_frame_size)) != SR_OK)
return TRUE;