+ const struct rdtech_dps_model *model;
+ struct sr_sw_limits limits;
+ int expecting_registers;
+};
+
+enum rdtech_dps_register {
+ REG_USET = 0x00, /* Mirror of 0x50 */
+ REG_ISET = 0x01, /* Mirror of 0x51 */
+ REG_UOUT = 0x02,
+ REG_IOUT = 0x03,
+ REG_POWER = 0x04,
+ REG_UIN = 0x05,
+ REG_LOCK = 0x06,
+ REG_PROTECT = 0x07,
+ REG_CV_CC = 0x08,
+ REG_ENABLE = 0x09,
+ REG_BACKLIGHT = 0x0A, /* Mirror of 0x55 */
+ REG_MODEL = 0x0B,
+ REG_VERSION = 0x0C,
+
+ REG_PRESET = 0x23, /* Loads a preset into preset 0. */
+
+/*
+ * Add (preset * 0x10) to each of the following, for preset 1-9.
+ * Preset 0 regs below are the active output settings.
+ */
+ PRE_USET = 0x50,
+ PRE_ISET = 0x51,
+ PRE_OVPSET = 0x52,
+ PRE_OCPSET = 0x53,
+ PRE_OPPSET = 0x54,
+ PRE_BACKLIGHT = 0x55,
+ PRE_DISABLE = 0x56, /* Disable output if 0 is copied here from a preset (1 is no change). */
+ PRE_BOOT = 0x57, /* Enable output at boot if 1. */
+};
+
+enum rdtech_dps_state {
+ STATE_NORMAL = 0,
+ STATE_OVP = 1,
+ STATE_OCP = 2,
+ STATE_OPP = 3,