+ /* If we are only digital or only analog print a warning that the fractional
+ * divisors aren't a true PLL fractional feedback loop and thus could have
+ * sample to sample variation. These warnings of course assume that the
+ * device is programmed with the expected ratios but non PICO
+ * implementations, or PICO implementations that use different divisors
+ * could avoid. This generally won't be a problem because most of the
+ * sample_rate pulldown values are integer divisors. */
+ if ((a_enabled > 0) && (48000000ULL % (devc->sample_rate * a_enabled)))
+ sr_warn("WARN: Non integer ADC divisor of 48Mhz clock for sample " \
+ "rate %lu may cause sample to sample variability.",
+ devc->sample_rate);
+ if ((d_enabled > 0) && (120000000ULL % (devc->sample_rate)))
+ sr_warn("WARN: Non integer PIO divisor of 120Mhz for sample rate " \
+ "%lu may cause sample to sample variability.", devc->sample_rate);
+
+ sprintf(tmpstr, "L%" PRIu64 "\n", devc->limit_samples);