-/* registers for control request 32: */
-#define CTRL_RUN 0x00
-#define CTRL_PWM_EN 0x02
-#define CTRL_BULK 0x10 /* can be read to get 12 byte sampling_info (III) */
-#define CTRL_SAMPLING 0x20
-#define CTRL_TRIGGER 0x30
-#define CTRL_THRESHOLD 0x48
-#define CTRL_PWM1 0x70
-#define CTRL_PWM2 0x78
+/* usb vendor class control requests to the cypress FX2 microcontroller */
+#define CMD_EEPROM 0xa2 /* ctrl_in reads, ctrl_out writes */
+#define CMD_FPGA_INIT 0x50 /* used before and after FPGA bitstream loading */
+#define CMD_FPGA_SPI 0x20 /* access registers in the FPGA over SPI bus, ctrl_in reads, ctrl_out writes */
+#define CMD_FPGA_ENABLE 0x10
+#define CMD_BULK_RESET 0x38 /* flush FX2 usb endpoint 6 IN fifos */
+#define CMD_BULK_START 0x30 /* begin transfer of capture data via usb endpoint 6 IN */
+#define CMD_KAUTH 0x60 /* communicate with authentication ic U10, not used */
+
+/*
+ * fpga spi register addresses for control request CMD_FPGA_SPI:
+ * There are around 60 byte-wide registers within the fpga and
+ * these are the base addresses used for accessing them.
+ * On the spi bus, the msb of the address byte is set for read
+ * and cleared for write, but that is handled by the fx2 mcu
+ * as appropriate. In this driver code just use IN transactions
+ * to read, OUT to write.
+ */
+#define REG_RUN 0x00 /* read capture status, write capture start */
+#define REG_PWM_EN 0x02 /* user pwm channels on/off */
+#define REG_CAPT_MODE 0x03 /* set to 0x00 for capture to sdram, 0x01 bypass sdram for streaming */
+#define REG_BULK 0x08 /* write start address and number of bytes for capture data bulk upload */
+#define REG_SAMPLING 0x10 /* write capture config, read capture data location in sdram */
+#define REG_TRIGGER 0x20 /* write level and edge trigger config */
+#define REG_THRESHOLD 0x68 /* write two pwm configs to control input threshold dac */
+#define REG_PWM1 0x70 /* write config for user pwm1 */
+#define REG_PWM2 0x78 /* write config for user pwm2 */