+/*
+ * The hardware uses a (model dependent) 100/200/500MHz base clock and
+ * a 16bit divider (common across all models). The range from 10kHz to
+ * 100/200/500MHz should be applicable to all devices. High rates may
+ * suffer from coarse resolution (e.g. in the "500MHz div 2" case) and
+ * may not provide the desired 1/2/5 steps. This is not an issue now,
+ * the 500MHz model is not supported yet by this driver.
+ */
+