+#define DEV_CAPS_AX_ANALOG (1 << DEV_CAPS_AX_ANALOG_POS)
+
+#define DSLOGIC_FPGA_FIRMWARE_5V "dreamsourcelab-dslogic-fpga-5v.fw"
+#define DSLOGIC_FPGA_FIRMWARE_3V3 "dreamsourcelab-dslogic-fpga-3v3.fw"
+#define DSCOPE_FPGA_FIRMWARE "dreamsourcelab-dscope-fpga.fw"
+#define DSLOGIC_PRO_FPGA_FIRMWARE "dreamsourcelab-dslogic-pro-fpga.fw"
+
+/* Protocol commands */
+#define CMD_GET_FW_VERSION 0xb0
+#define CMD_START 0xb1
+#define CMD_GET_REVID_VERSION 0xb2
+
+#define CMD_START_FLAGS_CLK_CTL2_POS 4
+#define CMD_START_FLAGS_WIDE_POS 5
+#define CMD_START_FLAGS_CLK_SRC_POS 6
+
+#define CMD_START_FLAGS_CLK_CTL2 (1 << CMD_START_FLAGS_CLK_CTL2_POS)
+#define CMD_START_FLAGS_SAMPLE_8BIT (0 << CMD_START_FLAGS_WIDE_POS)
+#define CMD_START_FLAGS_SAMPLE_16BIT (1 << CMD_START_FLAGS_WIDE_POS)
+
+#define CMD_START_FLAGS_CLK_30MHZ (0 << CMD_START_FLAGS_CLK_SRC_POS)
+#define CMD_START_FLAGS_CLK_48MHZ (1 << CMD_START_FLAGS_CLK_SRC_POS)