+ acq = devc->acquisition;
+
+ if (devc->limit_msec > 0) {
+ acq->duration_max = devc->limit_msec;
+ sr_info("Acquisition time limit %" PRIu64 " ms.",
+ devc->limit_msec);
+ } else
+ acq->duration_max = MAX_LIMIT_MSEC;
+
+ if (devc->limit_samples > 0) {
+ acq->samples_max = devc->limit_samples;
+ sr_info("Acquisition sample count limit %" PRIu64 ".",
+ devc->limit_samples);
+ } else
+ acq->samples_max = MAX_LIMIT_SAMPLES;
+
+ if (devc->cfg_clock_source == CLOCK_INTERNAL) {
+ sr_info("Internal clock, samplerate %" PRIu64 ".",
+ devc->samplerate);
+ if (devc->samplerate == 0)
+ return SR_ERR_BUG;
+ /* At 125 MHz, the clock divider is bypassed. */
+ acq->bypass_clockdiv = (devc->samplerate > SR_MHZ(100));
+
+ /* If only one of the limits is set, derive the other one. */
+ if (devc->limit_msec == 0 && devc->limit_samples > 0)
+ acq->duration_max = devc->limit_samples
+ * 1000 / devc->samplerate + 1;
+ else if (devc->limit_samples == 0 && devc->limit_msec > 0)
+ acq->samples_max = devc->limit_msec
+ * devc->samplerate / 1000;
+ } else {
+ acq->bypass_clockdiv = TRUE;
+
+ if (devc->cfg_clock_edge == EDGE_NEGATIVE)
+ sr_info("External clock, falling edge.");
+ else
+ sr_info("External clock, rising edge.");
+ }