+ struct acquisition_state *acq;
+ unsigned int mem_fill;
+ unsigned int flags;
+
+ devc = sdi->priv;
+ acq = devc->acquisition;
+
+ if (acq->xfer_in->actual_length != CAP_STAT_LEN * 8) {
+ sr_err("Received size %d doesn't match expected size %d.",
+ acq->xfer_in->actual_length, CAP_STAT_LEN * 8);
+ devc->transfer_error = TRUE;
+ return;
+ }
+
+ /* TODO: Find out the actual bit width of these fields as stored
+ * in the FPGA. These fields are definitely less than 64 bit wide
+ * internally, and the unused bits occasionally even contain garbage.
+ */
+ mem_fill = LWLA_TO_UINT32(acq->xfer_buf_in[0]);
+ duration = LWLA_TO_UINT32(acq->xfer_buf_in[4]);
+ flags = LWLA_TO_UINT32(acq->xfer_buf_in[8]) & STATUS_FLAG_MASK;
+
+ /* The LWLA1034 runs at 125 MHz if the clock divider is bypassed.
+ * However, the time base used for the duration is apparently not
+ * adjusted for this "boost" mode. Whereas normally the duration
+ * unit is 1 ms, it is 0.8 ms when the clock divider is bypassed.
+ * As 0.8 = 100 MHz / 125 MHz, it seems that the internal cycle
+ * counter period is the same as at the 100 MHz setting.
+ */
+ if (acq->bypass_clockdiv)
+ acq->duration_now = duration * 4 / 5;
+ else
+ acq->duration_now = duration;
+
+ sr_spew("Captured %u words, %" PRIu64 " ms, flags 0x%02X.",
+ mem_fill, acq->duration_now, flags);
+
+ if ((flags & STATUS_TRIGGERED) > (acq->capture_flags & STATUS_TRIGGERED))
+ sr_info("Capture triggered.");
+
+ acq->capture_flags = flags;
+
+ if (acq->duration_now >= acq->duration_max) {
+ sr_dbg("Time limit reached, stopping capture.");
+ issue_stop_capture(sdi);
+ return;
+ }
+ devc->state = STATE_STATUS_WAIT;
+
+ if ((acq->capture_flags & STATUS_TRIGGERED) == 0) {
+ sr_spew("Waiting for trigger.");
+ } else if ((acq->capture_flags & STATUS_MEM_AVAIL) == 0) {
+ sr_dbg("Capture memory filled.");
+ request_capture_length(sdi);
+ } else if ((acq->capture_flags & STATUS_CAPTURING) != 0) {
+ sr_spew("Sampling in progress.");
+ }
+}
+
+/* Issue a capture buffer read request as an asynchronous USB transfer.
+ * The address and size of the memory area to read are derived from the
+ * current acquisition state.
+ */
+static void request_read_mem(const struct sr_dev_inst *sdi)
+{
+ struct dev_context *devc;
+ struct acquisition_state *acq;
+ size_t count;
+
+ devc = sdi->priv;
+ acq = devc->acquisition;
+
+ if (acq->mem_addr_next >= acq->mem_addr_stop)
+ return;
+
+ /* Always read a multiple of 8 device words. */
+ count = (acq->mem_addr_stop - acq->mem_addr_next + 7) / 8 * 8;
+ count = MIN(count, READ_CHUNK_LEN);
+
+ acq->xfer_buf_out[0] = LWLA_WORD(CMD_READ_MEM);
+ acq->xfer_buf_out[1] = LWLA_WORD_0(acq->mem_addr_next);
+ acq->xfer_buf_out[2] = LWLA_WORD_1(acq->mem_addr_next);
+ acq->xfer_buf_out[3] = LWLA_WORD_0(count);
+ acq->xfer_buf_out[4] = LWLA_WORD_1(count);
+
+ acq->xfer_out->length = 5 * sizeof(uint16_t);
+
+ if (submit_transfer(devc, acq->xfer_out) == SR_OK) {
+ acq->mem_addr_next += count;
+ devc->state = STATE_READ_REQUEST;
+ }
+}
+
+/* Demangle and decompress incoming sample data from the capture buffer.
+ * The data chunk is taken from the acquisition state, and is expected to
+ * contain a multiple of 8 device words.
+ * All data currently in the acquisition buffer will be processed. Packets
+ * of decoded samples are sent off to the session bus whenever the output
+ * buffer becomes full while decoding.
+ */
+static int process_sample_data(const struct sr_dev_inst *sdi)
+{
+ uint64_t sample;
+ uint64_t high_nibbles;
+ uint64_t word;
+ struct dev_context *devc;
+ struct acquisition_state *acq;
+ uint8_t *out_p;
+ uint32_t *slice;
+ struct sr_datafeed_packet packet;
+ struct sr_datafeed_logic logic;
+ size_t expect_len;
+ size_t actual_len;
+ size_t out_max_samples;
+ size_t out_run_samples;
+ size_t ri;
+ size_t in_words_left;
+ size_t si;
+
+ devc = sdi->priv;
+ acq = devc->acquisition;
+
+ if (acq->mem_addr_done >= acq->mem_addr_stop
+ || acq->samples_done >= acq->samples_max)
+ return SR_OK;
+
+ in_words_left = MIN(acq->mem_addr_stop - acq->mem_addr_done,
+ READ_CHUNK_LEN);
+ expect_len = LWLA1034_MEMBUF_LEN(in_words_left) * sizeof(uint32_t);
+ actual_len = acq->xfer_in->actual_length;
+
+ if (actual_len != expect_len) {
+ sr_err("Received size %zu does not match expected size %zu.",
+ actual_len, expect_len);
+ devc->transfer_error = TRUE;
+ return SR_ERR;
+ }
+ acq->mem_addr_done += in_words_left;
+
+ /* Prepare session packet. */
+ packet.type = SR_DF_LOGIC;
+ packet.payload = &logic;
+ logic.unitsize = UNIT_SIZE;
+ logic.data = acq->out_packet;
+
+ slice = acq->xfer_buf_in;
+ si = 0; /* word index within slice */
+
+ for (;;) {
+ /* Calculate number of samples to write into packet. */
+ out_max_samples = MIN(acq->samples_max - acq->samples_done,
+ PACKET_LENGTH - acq->out_index);
+ out_run_samples = MIN(acq->run_len, out_max_samples);
+
+ /* Expand run-length samples into session packet. */
+ sample = acq->sample;
+ out_p = &acq->out_packet[acq->out_index * UNIT_SIZE];
+
+ for (ri = 0; ri < out_run_samples; ++ri) {
+ out_p[0] = sample & 0xFF;
+ out_p[1] = (sample >> 8) & 0xFF;
+ out_p[2] = (sample >> 16) & 0xFF;
+ out_p[3] = (sample >> 24) & 0xFF;
+ out_p[4] = (sample >> 32) & 0xFF;
+ out_p += UNIT_SIZE;
+ }
+ acq->run_len -= out_run_samples;
+ acq->out_index += out_run_samples;
+ acq->samples_done += out_run_samples;
+
+ /* Packet full or sample count limit reached? */
+ if (out_run_samples == out_max_samples) {
+ logic.length = acq->out_index * UNIT_SIZE;
+ sr_session_send(sdi, &packet);
+ acq->out_index = 0;
+
+ if (acq->samples_done >= acq->samples_max)
+ return SR_OK; /* sample limit reached */
+ if (acq->run_len > 0)
+ continue; /* need another packet */
+ }
+
+ if (in_words_left == 0)
+ break; /* done with current chunk */
+
+ /* Now work on the current slice. */
+ high_nibbles = LWLA_TO_UINT32(slice[8]);
+ word = LWLA_TO_UINT32(slice[si]);
+ word |= (high_nibbles << (4 * si + 4)) & ((uint64_t)0xF << 32);
+
+ if (acq->rle == RLE_STATE_DATA) {
+ acq->sample = word & ALL_CHANNELS_MASK;
+ acq->run_len = ((word >> NUM_CHANNELS) & 1) + 1;
+ if (word & RLE_FLAG_LEN_FOLLOWS)
+ acq->rle = RLE_STATE_LEN;
+ } else {
+ acq->run_len += word << 1;
+ acq->rle = RLE_STATE_DATA;
+ }
+
+ /* Move to next word. */
+ si = (si + 1) % 8;
+ if (si == 0)
+ slice += 9;
+ --in_words_left;
+ }
+
+ /* Send out partially filled packet if this was the last chunk. */
+ if (acq->mem_addr_done >= acq->mem_addr_stop && acq->out_index > 0) {
+ logic.length = acq->out_index * UNIT_SIZE;
+ sr_session_send(sdi, &packet);
+ acq->out_index = 0;
+ }
+ return SR_OK;
+}
+
+/* Finish an acquisition session. This sends the end packet to the session
+ * bus and removes the listener for asynchronous USB transfers.
+ */
+static void end_acquisition(struct sr_dev_inst *sdi)
+{
+ struct drv_context *drvc;
+ struct dev_context *devc;
+ struct sr_datafeed_packet packet;
+
+ drvc = sdi->driver->priv;
+ devc = sdi->priv;
+
+ if (devc->state == STATE_IDLE)
+ return;
+
+ devc->state = STATE_IDLE;
+
+ /* Remove USB file descriptors from polling. */
+ usb_source_remove(drvc->sr_ctx);
+
+ packet.type = SR_DF_END;
+ sr_session_send(sdi, &packet);
+
+ lwla_free_acquisition_state(devc->acquisition);
+ devc->acquisition = NULL;
+
+ sdi->status = SR_ST_ACTIVE;
+}
+
+/* USB output transfer completion callback.
+ */
+static void receive_transfer_out(struct libusb_transfer *transfer)
+{
+ struct sr_dev_inst *sdi;
+ struct dev_context *devc;
+
+ sdi = transfer->user_data;
+ devc = sdi->priv;
+
+ if (transfer->status != LIBUSB_TRANSFER_COMPLETED) {
+ sr_err("Transfer to device failed: %d.", transfer->status);
+ devc->transfer_error = TRUE;
+ return;
+ }
+
+ if (devc->reg_write_pos < devc->reg_write_len) {
+ issue_next_write_reg(sdi);
+ } else {
+ switch (devc->state) {
+ case STATE_START_CAPTURE:
+ devc->state = STATE_STATUS_WAIT;
+ break;
+ case STATE_STATUS_REQUEST:
+ devc->state = STATE_STATUS_RESPONSE;
+ submit_transfer(devc, devc->acquisition->xfer_in);
+ break;
+ case STATE_STOP_CAPTURE:
+ if (sdi->status == SR_ST_ACTIVE)
+ request_capture_length(sdi);
+ else
+ end_acquisition(sdi);
+ break;
+ case STATE_LENGTH_REQUEST:
+ devc->state = STATE_LENGTH_RESPONSE;
+ submit_transfer(devc, devc->acquisition->xfer_in);
+ break;
+ case STATE_READ_PREPARE:
+ request_read_mem(sdi);
+ break;
+ case STATE_READ_REQUEST:
+ devc->state = STATE_READ_RESPONSE;
+ submit_transfer(devc, devc->acquisition->xfer_in);
+ break;
+ case STATE_READ_END:
+ end_acquisition(sdi);
+ break;
+ default:
+ sr_err("Unexpected device state %d.", devc->state);
+ break;
+ }
+ }
+}
+
+/* USB input transfer completion callback.
+ */
+static void receive_transfer_in(struct libusb_transfer *transfer)
+{
+ struct sr_dev_inst *sdi;
+ struct dev_context *devc;
+ struct acquisition_state *acq;
+
+ sdi = transfer->user_data;
+ devc = sdi->priv;
+ acq = devc->acquisition;
+
+ if (transfer->status != LIBUSB_TRANSFER_COMPLETED) {
+ sr_err("Transfer from device failed: %d.", transfer->status);
+ devc->transfer_error = TRUE;
+ return;
+ }
+
+ switch (devc->state) {
+ case STATE_STATUS_RESPONSE:
+ process_capture_status(sdi);
+ break;
+ case STATE_LENGTH_RESPONSE:
+ process_capture_length(sdi);
+ break;
+ case STATE_READ_RESPONSE:
+ if (process_sample_data(sdi) == SR_OK
+ && acq->mem_addr_next < acq->mem_addr_stop
+ && acq->samples_done < acq->samples_max)
+ request_read_mem(sdi);
+ else
+ issue_read_end(sdi);
+ break;
+ default:
+ sr_err("Unexpected device state %d.", devc->state);
+ break;
+ }
+}
+
+/* Initialize the LWLA. This downloads a bitstream into the FPGA
+ * and executes a simple device test sequence.
+ */
+SR_PRIV int lwla_init_device(const struct sr_dev_inst *sdi)
+{
+ struct dev_context *devc;
+ int ret;
+ uint32_t value;
+
+ devc = sdi->priv;
+
+ /* Force reload of bitstream */
+ devc->cur_clock_config = CONF_CLOCK_NONE;
+
+ ret = lwla_set_clock_config(sdi);
+
+ if (ret != SR_OK)
+ return ret;
+
+ ret = lwla_write_reg(sdi->conn, REG_CMD_CTRL2, 100);
+ if (ret != SR_OK)
+ return ret;
+
+ ret = lwla_read_reg(sdi->conn, REG_CMD_CTRL1, &value);
+ if (ret != SR_OK)
+ return ret;
+ sr_dbg("Received test word 0x%08X back.", value);
+ if (value != 0x12345678)
+ return SR_ERR;
+
+ ret = lwla_read_reg(sdi->conn, REG_CMD_CTRL4, &value);
+ if (ret != SR_OK)
+ return ret;
+ sr_dbg("Received test word 0x%08X back.", value);
+ if (value != 0x12345678)
+ return SR_ERR;
+
+ ret = lwla_read_reg(sdi->conn, REG_CMD_CTRL3, &value);
+ if (ret != SR_OK)
+ return ret;
+ sr_dbg("Received test word 0x%08X back.", value);
+ if (value != 0x87654321)
+ return SR_ERR;
+
+ return ret;
+}
+
+SR_PRIV int lwla_convert_trigger(const struct sr_dev_inst *sdi)
+{
+ struct dev_context *devc;
+ struct sr_trigger *trigger;
+ struct sr_trigger_stage *stage;
+ struct sr_trigger_match *match;
+ const GSList *l, *m;
+ uint64_t channel_index;
+
+ devc = sdi->priv;
+
+ devc->trigger_mask = 0;
+ devc->trigger_values = 0;
+ devc->trigger_edge_mask = 0;
+
+ if (!(trigger = sr_session_trigger_get()))
+ return SR_OK;
+
+ if (g_slist_length(trigger->stages) > 1) {
+ sr_err("This device only supports 1 trigger stage.");
+ return SR_ERR;
+ }
+
+ for (l = trigger->stages; l; l = l->next) {
+ stage = l->data;
+ for (m = stage->matches; m; m = m->next) {
+ match = m->data;
+ if (!match->channel->enabled)
+ /* Ignore disabled channels with a trigger. */
+ continue;
+ channel_index = 1 << match->channel->index;
+ devc->trigger_mask |= channel_index;
+ switch (match->match) {
+ case SR_TRIGGER_ONE:
+ devc->trigger_values |= channel_index;
+ break;
+ case SR_TRIGGER_RISING:
+ devc->trigger_values |= channel_index;
+ /* Fall through for edge mask. */
+ case SR_TRIGGER_FALLING:
+ devc->trigger_edge_mask |= channel_index;
+ break;
+ }
+ }
+ }
+
+ return SR_OK;
+}
+
+/* Select the LWLA clock configuration. If the clock source changed from
+ * the previous setting, this will download a new bitstream to the FPGA.
+ */
+SR_PRIV int lwla_set_clock_config(const struct sr_dev_inst *sdi)
+{
+ struct dev_context *devc;
+ int ret;
+ enum clock_config choice;
+
+ devc = sdi->priv;
+
+ if (sdi->status == SR_ST_INACTIVE)
+ choice = CONF_CLOCK_NONE;
+ else if (devc->cfg_clock_source == CLOCK_INTERNAL)
+ choice = CONF_CLOCK_INT;
+ else if (devc->cfg_clock_edge == EDGE_POSITIVE)
+ choice = CONF_CLOCK_EXT_RISE;
+ else
+ choice = CONF_CLOCK_EXT_FALL;
+
+ if (choice != devc->cur_clock_config) {
+ devc->cur_clock_config = CONF_CLOCK_NONE;
+ ret = lwla_send_bitstream(sdi->conn, bitstream_map[choice]);
+ if (ret == SR_OK)
+ devc->cur_clock_config = choice;
+ return ret;
+ }
+ return SR_OK;
+}
+
+/* Configure the LWLA in preparation for an acquisition session.
+ */
+SR_PRIV int lwla_setup_acquisition(const struct sr_dev_inst *sdi)
+{
+ struct dev_context *devc;
+ struct sr_usb_dev_inst *usb;
+ struct acquisition_state *acq;
+ struct regval_pair regvals[7];
+ int ret;
+
+ devc = sdi->priv;
+ usb = sdi->conn;
+ acq = devc->acquisition;
+
+ if (devc->limit_msec > 0) {
+ acq->duration_max = devc->limit_msec;
+ sr_info("Acquisition time limit %" PRIu64 " ms.",
+ devc->limit_msec);
+ } else
+ acq->duration_max = MAX_LIMIT_MSEC;
+
+ if (devc->limit_samples > 0) {
+ acq->samples_max = devc->limit_samples;
+ sr_info("Acquisition sample count limit %" PRIu64 ".",
+ devc->limit_samples);
+ } else
+ acq->samples_max = MAX_LIMIT_SAMPLES;
+
+ if (devc->cfg_clock_source == CLOCK_INTERNAL) {
+ sr_info("Internal clock, samplerate %" PRIu64 ".",
+ devc->samplerate);
+ if (devc->samplerate == 0)
+ return SR_ERR_BUG;
+ /* At 125 MHz, the clock divider is bypassed. */
+ acq->bypass_clockdiv = (devc->samplerate > SR_MHZ(100));
+
+ /* If only one of the limits is set, derive the other one. */
+ if (devc->limit_msec == 0 && devc->limit_samples > 0)
+ acq->duration_max = devc->limit_samples
+ * 1000 / devc->samplerate + 1;
+ else if (devc->limit_samples == 0 && devc->limit_msec > 0)
+ acq->samples_max = devc->limit_msec
+ * devc->samplerate / 1000;
+ } else {
+ acq->bypass_clockdiv = TRUE;
+
+ if (devc->cfg_clock_edge == EDGE_NEGATIVE)
+ sr_info("External clock, falling edge.");
+ else
+ sr_info("External clock, rising edge.");
+ }
+
+ regvals[0].reg = REG_MEM_CTRL2;
+ regvals[0].val = 2;
+
+ regvals[1].reg = REG_MEM_CTRL2;
+ regvals[1].val = 1;
+
+ regvals[2].reg = REG_CMD_CTRL2;
+ regvals[2].val = 10;
+
+ regvals[3].reg = REG_CMD_CTRL3;
+ regvals[3].val = 0x74;
+
+ regvals[4].reg = REG_CMD_CTRL4;
+ regvals[4].val = 0;
+
+ regvals[5].reg = REG_CMD_CTRL1;
+ regvals[5].val = 0;
+
+ regvals[6].reg = REG_DIV_BYPASS;
+ regvals[6].val = acq->bypass_clockdiv;
+
+ ret = lwla_write_regs(usb, regvals, G_N_ELEMENTS(regvals));
+ if (ret != SR_OK)
+ return ret;
+
+ return capture_setup(sdi);
+}
+
+/* Start the capture operation on the LWLA device. Beginning with this
+ * function, all USB transfers will be asynchronous until the end of the
+ * acquisition session.
+ */
+SR_PRIV int lwla_start_acquisition(const struct sr_dev_inst *sdi)
+{
+ struct dev_context *devc;
+ struct sr_usb_dev_inst *usb;
+ struct acquisition_state *acq;
+ struct regval_pair *regvals;
+
+ devc = sdi->priv;
+ usb = sdi->conn;
+ acq = devc->acquisition;
+
+ acq->duration_now = 0;
+ acq->mem_addr_fill = 0;
+ acq->capture_flags = 0;
+
+ libusb_fill_bulk_transfer(acq->xfer_out, usb->devhdl, EP_COMMAND,
+ (unsigned char *)acq->xfer_buf_out, 0,
+ &receive_transfer_out,
+ (struct sr_dev_inst *)sdi, USB_TIMEOUT);
+
+ libusb_fill_bulk_transfer(acq->xfer_in, usb->devhdl, EP_REPLY,
+ (unsigned char *)acq->xfer_buf_in,
+ sizeof acq->xfer_buf_in,
+ &receive_transfer_in,
+ (struct sr_dev_inst *)sdi, USB_TIMEOUT);
+
+ regvals = devc->reg_write_seq;
+
+ regvals[0].reg = REG_CMD_CTRL2;
+ regvals[0].val = 10;
+
+ regvals[1].reg = REG_CMD_CTRL3;
+ regvals[1].val = 1;
+
+ regvals[2].reg = REG_CMD_CTRL4;
+ regvals[2].val = 0;
+
+ regvals[3].reg = REG_CMD_CTRL1;
+ regvals[3].val = 0;
+
+ devc->reg_write_pos = 0;
+ devc->reg_write_len = 4;
+
+ devc->state = STATE_START_CAPTURE;
+
+ return issue_next_write_reg(sdi);
+}
+
+/* Allocate an acquisition state object.
+ */
+SR_PRIV struct acquisition_state *lwla_alloc_acquisition_state(void)
+{
+ struct acquisition_state *acq;
+
+ acq = g_try_new0(struct acquisition_state, 1);
+ if (!acq) {
+ sr_err("Acquisition state malloc failed.");
+ return NULL;
+ }
+
+ acq->xfer_in = libusb_alloc_transfer(0);
+ if (!acq->xfer_in) {
+ sr_err("Transfer malloc failed.");
+ g_free(acq);
+ return NULL;
+ }
+
+ acq->xfer_out = libusb_alloc_transfer(0);
+ if (!acq->xfer_out) {
+ sr_err("Transfer malloc failed.");
+ libusb_free_transfer(acq->xfer_in);
+ g_free(acq);
+ return NULL;
+ }
+
+ return acq;
+}
+
+/* Deallocate an acquisition state object.
+ */
+SR_PRIV void lwla_free_acquisition_state(struct acquisition_state *acq)
+{
+ if (acq) {
+ libusb_free_transfer(acq->xfer_out);
+ libusb_free_transfer(acq->xfer_in);
+ g_free(acq);
+ }
+}
+
+/* USB I/O source callback.
+ */
+SR_PRIV int lwla_receive_data(int fd, int revents, void *cb_data)
+{
+ struct sr_dev_inst *sdi;
+ struct dev_context *devc;
+ struct drv_context *drvc;
+ struct timeval tv;
+ int ret;