+SR_PRIV int logic16_setup_acquisition(const struct sr_dev_inst *sdi,
+ uint64_t samplerate, uint16_t channels)
+{
+ uint8_t clock_select, reg1, reg10;
+ uint64_t div;
+ int i, ret, nchan = 0;
+ struct dev_context *devc;
+
+ devc = sdi->priv;
+
+ if (samplerate == 0 || samplerate > MAX_SAMPLE_RATE) {
+ sr_err("Unable to sample at %" PRIu64 "Hz.", samplerate);
+ return SR_ERR;
+ }
+
+ if (BASE_CLOCK_0_FREQ % samplerate == 0 &&
+ (div = BASE_CLOCK_0_FREQ / samplerate) <= 256) {
+ clock_select = 0;
+ } else if (BASE_CLOCK_1_FREQ % samplerate == 0 &&
+ (div = BASE_CLOCK_1_FREQ / samplerate) <= 256) {
+ clock_select = 1;
+ } else {
+ sr_err("Unable to sample at %" PRIu64 "Hz.", samplerate);
+ return SR_ERR;
+ }
+
+ for (i = 0; i < 16; i++)
+ if (channels & (1U << i))
+ nchan++;
+
+ if ((nchan >= 13 && samplerate > MAX_13CH_SAMPLE_RATE) ||
+ (nchan >= 10 && samplerate > MAX_10CH_SAMPLE_RATE) ||
+ (nchan >= 8 && samplerate > MAX_8CH_SAMPLE_RATE) ||
+ (nchan >= 7 && samplerate > MAX_7CH_SAMPLE_RATE) ||
+ (nchan >= 4 && samplerate > MAX_4CH_SAMPLE_RATE)) {
+ sr_err("Unable to sample at %" PRIu64 "Hz "
+ "with this many channels.", samplerate);
+ return SR_ERR;
+ }
+
+ ret = upload_fpga_bitstream(sdi, devc->selected_voltage_range);
+ if (ret != SR_OK)
+ return ret;
+
+ if ((ret = read_fpga_register(sdi, 1, ®1)) != SR_OK)
+ return ret;
+
+ if (reg1 != 0x08) {
+ sr_dbg("Invalid state at acquisition setup: 0x%02x != 0x08.", reg1);
+ return SR_ERR;
+ }
+
+ if ((ret = write_fpga_register(sdi, 1, 0x40)) != SR_OK)
+ return ret;
+
+ if ((ret = write_fpga_register(sdi, 10, clock_select)) != SR_OK)
+ return ret;
+
+ if ((ret = write_fpga_register(sdi, 4, (uint8_t)(div - 1))) != SR_OK)
+ return ret;
+
+ if ((ret = write_fpga_register(sdi, 2, (uint8_t)(channels & 0xff))) != SR_OK)
+ return ret;
+
+ if ((ret = write_fpga_register(sdi, 3, (uint8_t)(channels >> 8))) != SR_OK)
+ return ret;
+
+ if ((ret = write_fpga_register(sdi, 1, 0x42)) != SR_OK)
+ return ret;
+
+ if ((ret = write_fpga_register(sdi, 1, 0x40)) != SR_OK)
+ return ret;
+
+ if ((ret = read_fpga_register(sdi, 1, ®1)) != SR_OK)
+ return ret;
+
+ if (reg1 != 0x48) {
+ sr_dbg("Invalid state at acquisition setup: 0x%02x != 0x48.", reg1);
+ return SR_ERR;
+ }
+
+ if ((ret = read_fpga_register(sdi, 10, ®10)) != SR_OK)
+ return ret;
+
+ if (reg10 != clock_select) {
+ sr_dbg("Invalid state at acquisition setup: 0x%02x != 0x%02x.",
+ reg10, clock_select);
+ return SR_ERR;
+ }
+
+ return SR_OK;
+}
+
+SR_PRIV int logic16_start_acquisition(const struct sr_dev_inst *sdi)
+{
+ static const uint8_t command[1] = {
+ COMMAND_START_ACQUISITION,
+ };
+ int ret;
+
+ if ((ret = do_ep1_command(sdi, command, 1, NULL, 0)) != SR_OK)
+ return ret;
+
+ return write_fpga_register(sdi, 1, 0x41);
+}
+
+SR_PRIV int logic16_abort_acquisition(const struct sr_dev_inst *sdi)
+{
+ static const uint8_t command[1] = {
+ COMMAND_ABORT_ACQUISITION_ASYNC,
+ };
+ int ret;
+ uint8_t reg1, reg8, reg9;
+
+ if ((ret = do_ep1_command(sdi, command, 1, NULL, 0)) != SR_OK)
+ return ret;
+
+ if ((ret = write_fpga_register(sdi, 1, 0x00)) != SR_OK)
+ return ret;
+
+ if ((ret = read_fpga_register(sdi, 1, ®1)) != SR_OK)
+ return ret;
+
+ if (reg1 != 0x08) {
+ sr_dbg("Invalid state at acquisition stop: 0x%02x != 0x08.", reg1);
+ return SR_ERR;
+ }
+
+ if ((ret = read_fpga_register(sdi, 8, ®8)) != SR_OK)
+ return ret;
+
+ if ((ret = read_fpga_register(sdi, 9, ®9)) != SR_OK)
+ return ret;
+
+ return SR_OK;
+}
+
+SR_PRIV int logic16_init_device(const struct sr_dev_inst *sdi)