+SR_PRIV int mso_configure_trigger(const struct sr_dev_inst *sdi)
+{
+ struct dev_context *devc = sdi->priv;
+ uint16_t threshold_value = mso_calc_raw_from_mv(devc);
+
+ threshold_value = 0x153C;
+ uint8_t trigger_config = 0;
+
+ if (devc->trigger_slope)
+ trigger_config |= 0x04; //Trigger on falling edge
+
+ switch (devc->trigger_outsrc) {
+ case 1:
+ trigger_config |= 0x00; //Trigger pulse output
+ break;
+ case 2:
+ trigger_config |= 0x08; //PWM DAC from the pattern generator buffer
+ break;
+ case 3:
+ trigger_config |= 0x18; //White noise
+ break;
+ }
+
+ switch (devc->trigger_chan) {
+ case 0:
+ trigger_config |= 0x00; //DSO level trigger //b00000000
+ break;
+ case 1:
+ trigger_config |= 0x20; //DSO level trigger & width < trigger_width
+ break;
+ case 2:
+ trigger_config |= 0x40; //DSO level trigger & width >= trigger_width
+ break;
+ case 3:
+ trigger_config |= 0x60; //LA combination trigger
+ break;
+ }
+
+ //Last bit of trigger config reg 4 needs to be 1 for trigger enable,
+ //otherwise the trigger is not enabled
+ if (devc->use_trigger)
+ trigger_config |= 0x80;
+
+ uint16_t ops[18];
+ ops[0] = mso_trans(3, threshold_value & 0xff);
+ //The trigger_config also holds the 2 MSB bits from the threshold value
+ ops[1] = mso_trans(4, trigger_config | ((threshold_value >> 8) & 0x03));
+ ops[2] = mso_trans(5, devc->la_trigger);
+ ops[3] = mso_trans(6, devc->la_trigger_mask);
+ ops[4] = mso_trans(7, devc->trigger_holdoff[0]);
+ ops[5] = mso_trans(8, devc->trigger_holdoff[1]);
+
+ ops[6] = mso_trans(11,
+ devc->dso_trigger_width /
+ SR_HZ_TO_NS(devc->cur_rate));
+
+ /* Select the SPI/I2C trigger config bank */
+ ops[7] = mso_trans(REG_CTL2, (devc->ctlbase2 | BITS_CTL2_BANK(2)));
+ /* Configure the SPI/I2C protocol trigger */
+ ops[8] = mso_trans(REG_PT_WORD(0), devc->protocol_trigger.word[0]);
+ ops[9] = mso_trans(REG_PT_WORD(1), devc->protocol_trigger.word[1]);
+ ops[10] = mso_trans(REG_PT_WORD(2), devc->protocol_trigger.word[2]);
+ ops[11] = mso_trans(REG_PT_WORD(3), devc->protocol_trigger.word[3]);
+ ops[12] = mso_trans(REG_PT_MASK(0), devc->protocol_trigger.mask[0]);
+ ops[13] = mso_trans(REG_PT_MASK(1), devc->protocol_trigger.mask[1]);
+ ops[14] = mso_trans(REG_PT_MASK(2), devc->protocol_trigger.mask[2]);
+ ops[15] = mso_trans(REG_PT_MASK(3), devc->protocol_trigger.mask[3]);
+ ops[16] = mso_trans(REG_PT_SPIMODE, devc->protocol_trigger.spimode);
+ /* Select the default config bank */
+ ops[17] = mso_trans(REG_CTL2, devc->ctlbase2);
+
+ return mso_send_control_message(devc->serial, ARRAY_AND_SIZE(ops));
+}
+
+SR_PRIV int mso_configure_threshold_level(const struct sr_dev_inst *sdi)
+{
+ struct dev_context *devc = sdi->priv;
+
+ return mso_dac_out(sdi, la_threshold_map[devc->la_threshold]);
+}
+
+SR_PRIV int mso_read_buffer(struct sr_dev_inst *sdi)
+{
+ uint16_t ops[] = { mso_trans(REG_BUFFER, 0) };
+ struct dev_context *devc = sdi->priv;
+
+ sr_dbg("Requesting buffer dump.");
+ return mso_send_control_message(devc->serial, ARRAY_AND_SIZE(ops));
+}
+
+SR_PRIV int mso_arm(const struct sr_dev_inst *sdi)
+{
+ struct dev_context *devc = sdi->priv;
+ uint16_t ops[] = {
+ mso_trans(REG_CTL1, devc->ctlbase1 | BIT_CTL1_RESETFSM),
+ mso_trans(REG_CTL1, devc->ctlbase1 | BIT_CTL1_ARM),
+ mso_trans(REG_CTL1, devc->ctlbase1),
+ };
+
+ sr_dbg("Requesting trigger arm.");
+ return mso_send_control_message(devc->serial, ARRAY_AND_SIZE(ops));
+}
+
+SR_PRIV int mso_force_capture(struct sr_dev_inst *sdi)
+{
+ struct dev_context *devc = sdi->priv;
+ uint16_t ops[] = {
+ mso_trans(REG_CTL1, devc->ctlbase1 | 8),
+ mso_trans(REG_CTL1, devc->ctlbase1),
+ };
+
+ sr_dbg("Requesting forced capture.");
+ return mso_send_control_message(devc->serial, ARRAY_AND_SIZE(ops));
+}
+
+SR_PRIV int mso_dac_out(const struct sr_dev_inst *sdi, uint16_t val)
+{
+ struct dev_context *devc = sdi->priv;
+ uint16_t ops[] = {
+ mso_trans(REG_DAC1, (val >> 8) & 0xff),
+ mso_trans(REG_DAC2, val & 0xff),
+ mso_trans(REG_CTL1, devc->ctlbase1 | BIT_CTL1_RESETADC),
+ };
+
+ sr_dbg("Setting dac word to 0x%x.", val);
+ return mso_send_control_message(devc->serial, ARRAY_AND_SIZE(ops));
+}
+
+SR_PRIV inline uint16_t mso_calc_raw_from_mv(struct dev_context * devc)
+{
+ return (uint16_t) (0x200 -
+ ((devc->dso_trigger_voltage / devc->dso_probe_attn) /
+ devc->vbit));
+}
+
+SR_PRIV int mso_parse_serial(const char *iSerial, const char *iProduct,
+ struct dev_context *devc)
+{
+ unsigned int u1, u2, u3, u4, u5, u6;
+
+ (void)iProduct;
+
+ /* FIXME: This code is in the original app, but I think its
+ * used only for the GUI */
+ /* if (strstr(iProduct, "REV_02") || strstr(iProduct, "REV_03"))
+ devc->num_sample_rates = 0x16;
+ else
+ devc->num_sample_rates = 0x10; */
+
+ /* parse iSerial */
+ if (iSerial[0] != '4' || sscanf(iSerial, "%5u%3u%3u%1u%1u%6u",
+ &u1, &u2, &u3, &u4, &u5, &u6) != 6)
+ return SR_ERR;
+ devc->hwmodel = u4;
+ devc->hwrev = u5;
+ devc->vbit = u1 / 10000;
+ if (devc->vbit == 0)
+ devc->vbit = 4.19195;
+ devc->dac_offset = u2;
+ if (devc->dac_offset == 0)
+ devc->dac_offset = 0x1ff;
+ devc->offset_range = u3;
+ if (devc->offset_range == 0)
+ devc->offset_range = 0x17d;
+
+ /*
+ * FIXME: There is more code on the original software to handle
+ * bigger iSerial strings, but as I can't test on my device
+ * I will not implement it yet
+ */
+
+ return SR_OK;
+}
+