+/* Force the FPGA to reboot. */
+static uint8_t suicide[] = {
+ 0x84, 0x84, 0x88, 0x84, 0x88, 0x84, 0x88, 0x84,
+};
+
+/* Prepare to upload firmware (FPGA specific). */
+static uint8_t init[] = {
+ 0x03, 0x03, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01,
+};
+
+/* Initialize the logic analyzer mode. */
+static uint8_t logic_mode_start[] = {
+ 0x00, 0x40, 0x0f, 0x25, 0x35, 0x40,
+ 0x2a, 0x3a, 0x40, 0x03, 0x20, 0x38,
+};
+
+static const char *firmware_files[] =
+{
+ "asix-sigma-50.fw", /* 50 MHz, supports 8 bit fractions */
+ "asix-sigma-100.fw", /* 100 MHz */
+ "asix-sigma-200.fw", /* 200 MHz */
+ "asix-sigma-50sync.fw", /* Asynchronous sampling */
+ "asix-sigma-phasor.fw", /* Frequency counter */
+};
+