+ int i,j;
+ uint16_t masks[2] = { 0, 0 };
+
+ memset(lut, 0, sizeof(struct triggerlut));
+
+ /* Contant for simple triggers. */
+ lut->m4 = 0xa000;
+
+ /* Value/mask trigger support. */
+ build_lut_entry(ctx->trigger.simplevalue, ctx->trigger.simplemask,
+ lut->m2d);
+
+ /* Rise/fall trigger support. */
+ for (i = 0, j = 0; i < 16; ++i) {
+ if (ctx->trigger.risingmask & (1 << i) ||
+ ctx->trigger.fallingmask & (1 << i))
+ masks[j++] = 1 << i;
+ }
+
+ build_lut_entry(masks[0], masks[0], lut->m0d);
+ build_lut_entry(masks[1], masks[1], lut->m1d);
+
+ /* Add glue logic */
+ if (masks[0] || masks[1]) {
+ /* Transition trigger. */
+ if (masks[0] & ctx->trigger.risingmask)
+ add_trigger_function(OP_RISE, FUNC_OR, 0, 0, &lut->m3);
+ if (masks[0] & ctx->trigger.fallingmask)
+ add_trigger_function(OP_FALL, FUNC_OR, 0, 0, &lut->m3);
+ if (masks[1] & ctx->trigger.risingmask)
+ add_trigger_function(OP_RISE, FUNC_OR, 1, 0, &lut->m3);
+ if (masks[1] & ctx->trigger.fallingmask)
+ add_trigger_function(OP_FALL, FUNC_OR, 1, 0, &lut->m3);
+ } else {
+ /* Only value/mask trigger. */
+ lut->m3 = 0xffff;
+ }
+
+ /* Triggertype: event. */
+ lut->params.selres = 3;
+
+ return SR_OK;
+}
+
+static int hw_dev_acquisition_start(int dev_index, void *cb_data)
+{
+ struct sr_dev_inst *sdi;
+ struct context *ctx;
+ struct sr_datafeed_packet *packet;
+ struct sr_datafeed_header *header;
+ struct sr_datafeed_meta_logic meta;
+ struct clockselect_50 clockselect;
+ int frac, triggerpin, ret;
+ uint8_t triggerselect;
+ struct triggerinout triggerinout_conf;
+ struct triggerlut lut;
+
+ if (!(sdi = sr_dev_inst_get(dev_insts, dev_index)))
+ return SR_ERR;
+
+ ctx = sdi->priv;
+
+ /* If the samplerate has not been set, default to 200 kHz. */
+ if (ctx->cur_firmware == -1) {
+ if ((ret = set_samplerate(sdi, SR_KHZ(200))) != SR_OK)
+ return ret;
+ }
+
+ /* Enter trigger programming mode. */
+ sigma_set_register(WRITE_TRIGGER_SELECT1, 0x20, ctx);
+
+ /* 100 and 200 MHz mode. */
+ if (ctx->cur_samplerate >= SR_MHZ(100)) {
+ sigma_set_register(WRITE_TRIGGER_SELECT1, 0x81, ctx);
+
+ /* Find which pin to trigger on from mask. */
+ for (triggerpin = 0; triggerpin < 8; ++triggerpin)
+ if ((ctx->trigger.risingmask | ctx->trigger.fallingmask) &
+ (1 << triggerpin))
+ break;