- # DATA is shifted in the DAC on the falling CLK edge (MSB-first).
- # TODO: Handle various LOAD-/LDAC-controlled methods.
- if not (self.oldclk == 1 and clk == 0):
- self.oldclk = clk
- continue
-
- # The DAC has received a new bit, store it.
- self.bits.append(data)
-
- if self.state == 'IDLE':
- # Wait until we have read 11 bits, then parse them.
- l, s = len(self.bits), self.samplenum
- if l == 1:
- self.ss_dac = s
- elif l == 2:
- self.es_dac = self.ss_gain = s
- elif l == 3:
- self.es_gain = self.ss_value = s
- elif l == 11:
- self.es_value = s
- self.handle_11bits()
+ return True
+
+ def handle_falling_edge_load(self):
+ if not self.handle_11bits():
+ return
+ s, v, g = self.dac_select, self.dac_value, self.gain
+ self.put(self.samplenum, self.samplenum, self.out_ann,
+ [3, ['Falling edge on LOAD', 'LOAD fall', 'F']])
+ vref = self.options['vref_%s' % self.dac_select[3].lower()]
+ v = '%.2fV' % (vref * (v / 256) * self.gain)
+ if self.ldac == 0:
+ # If LDAC is low, the voltage is set immediately.
+ self.put(self.ss_dac, self.es_value, self.out_ann,
+ [7, ['Setting %s voltage to %s' % (s, v),
+ '%s=%s' % (s, v)]])
+ else:
+ # If LDAC is high, the voltage is not set immediately, but rather
+ # stored in a register. When LDAC goes low all four DAC voltages
+ # (DAC A/B/C/D) will be set at the same time.
+ self.put(self.ss_dac, self.es_value, self.out_ann,
+ [6, ['Setting %s register value to %s' % \
+ (s, v), '%s=%s' % (s, v)]])
+ # Save the last value the respective DAC was set to.
+ self.dacval[self.dac_select[-1]] = str(self.dac_value)
+ self.gains[self.dac_select[-1]] = self.gain
+
+ def handle_falling_edge_ldac(self):
+ self.put(self.samplenum, self.samplenum, self.out_ann,
+ [4, ['Falling edge on LDAC', 'LDAC fall', 'LDAC', 'L']])
+
+ # Don't emit any annotations if we didn't see any register writes.
+ if self.ss_dac_first is None:
+ return
+
+ # Calculate voltages based on Vref and the per-DAC gain.
+ dacval = {}
+ for key, val in self.dacval.items():
+ if val == '?':
+ dacval[key] = '?'