+ def handle_write_common(self, mosi, miso, ann):
+ # Write data bytes: Master asserts CS#, sends WRITE command, sends
+ # 3-byte address, writes >= 1 data bytes, de-asserts CS#.
+ if self.cmdstate == 1:
+ # Byte 1: Master sends command ID.
+ self.emit_cmd_byte()
+ if self.writestate == 0:
+ self.putc([Ann.WARN, ['Warning: WREN might be missing']])
+ elif self.cmdstate in (2, 3, 4):
+ # Bytes 2/3/4: Master sends write address (24bits, MSB-first).
+ self.emit_addr_bytes(mosi)
+ elif self.cmdstate >= 5:
+ # Bytes 5-x: Master writes data bytes (until CS# de-asserted).
+ self.es_field = self.es # Will be overwritten for each byte.
+ if self.cmdstate == 5:
+ self.ss_field = self.ss
+ self.on_end_transaction = lambda: self.output_data_block('Data', ann)
+ self.data.append(mosi)
+ self.cmdstate += 1
+
+ def handle_write1(self, mosi, miso):
+ self.handle_write_common(mosi, miso, Ann.WRITE1)
+
+ def handle_write2(self, mosi, miso):
+ self.handle_write_common(mosi, miso, Ann.WRITE2)
+