The data is _usually_ 8 bits (but can also be fewer or more bits).
Both data items are Python numbers (not strings), or None if the respective
The data is _usually_ 8 bits (but can also be fewer or more bits).
Both data items are Python numbers (not strings), or None if the respective
- probe was not supplied.
- - 'BITS': <data1>/<data2> contain a list of bit values in this MISO/MOSI data
+ channel was not supplied.
+ - 'BITS': <data1>/<data2> contain a list of bit values in this MOSI/MISO data
item, and for each of those also their respective start-/endsample numbers.
- 'CS CHANGE': <data1> is the old CS# pin value, <data2> is the new value.
item, and for each of those also their respective start-/endsample numbers.
- 'CS CHANGE': <data1> is the old CS# pin value, <data2> is the new value.
- Both data items are Python numbers (0/1), not strings.
+ Both data items are Python numbers (0/1), not strings. At the beginning of
+ the decoding a packet is generated with <data1> = None and <data2> being the
+ initial state of the CS# pin or None if the chip select pin is not supplied.
['CS-CHANGE', 1, 0]
['DATA', 0xff, 0x3a]
['BITS', [[1, 80, 82], [1, 83, 84], [1, 85, 86], [1, 87, 88],
['CS-CHANGE', 1, 0]
['DATA', 0xff, 0x3a]
['BITS', [[1, 80, 82], [1, 83, 84], [1, 85, 86], [1, 87, 88],
{'id': 'clk', 'name': 'CLK', 'desc': 'Clock'},
)
{'id': 'clk', 'name': 'CLK', 'desc': 'Clock'},
)
{'id': 'miso', 'name': 'MISO', 'desc': 'Master in, slave out'},
{'id': 'mosi', 'name': 'MOSI', 'desc': 'Master out, slave in'},
{'id': 'cs', 'name': 'CS#', 'desc': 'Chip-select'},
{'id': 'miso', 'name': 'MISO', 'desc': 'Master in, slave out'},
{'id': 'mosi', 'name': 'MOSI', 'desc': 'Master out, slave in'},
{'id': 'cs', 'name': 'CS#', 'desc': 'Chip-select'},
'values': (0, 1)},
{'id': 'cpha', 'desc': 'Clock phase', 'default': 0,
'values': (0, 1)},
'values': (0, 1)},
{'id': 'cpha', 'desc': 'Clock phase', 'default': 0,
'values': (0, 1)},
'default': 'msb-first', 'values': ('msb-first', 'lsb-first')},
'default': 'msb-first', 'values': ('msb-first', 'lsb-first')},
- {'id': 'wordsize', 'desc': 'Word size of SPI data', 'default': 8},
+ {'id': 'wordsize', 'desc': 'Word size', 'default': 8},
('mosi-bits', 'MOSI bits', (3,)),
('other', 'Other', (4,)),
)
('mosi-bits', 'MOSI bits', (3,)),
('other', 'Other', (4,)),
)
def metadata(self, key, value):
if key == srd.SRD_CONF_SAMPLERATE:
def metadata(self, key, value):
if key == srd.SRD_CONF_SAMPLERATE:
self.out_bitrate = self.register(srd.OUTPUT_META,
meta=(int, 'Bitrate', 'Bitrate during transfers'))
def putw(self, data):
self.out_bitrate = self.register(srd.OUTPUT_META,
meta=(int, 'Bitrate', 'Bitrate during transfers'))
def putw(self, data):
- self.put(self.startsample, self.samplenum, self.out_ann, data)
+ self.put(self.ss_block, self.samplenum, self.out_ann, data)
self.put(ss, es, self.out_python, ['BITS', si_bits, so_bits])
self.put(ss, es, self.out_python, ['DATA', si, so])
self.put(ss, es, self.out_python, ['BITS', si_bits, so_bits])
self.put(ss, es, self.out_python, ['DATA', si, so])
def handle_bit(self, miso, mosi, clk, cs):
# If this is the first bit of a dataword, save its sample number.
if self.bitcount == 0:
def handle_bit(self, miso, mosi, clk, cs):
# If this is the first bit of a dataword, save its sample number.
if self.bitcount == 0:
- self.startsample = self.samplenum
- self.cs_was_deasserted = False
- if self.have_cs:
- active_low = (self.options['cs_polarity'] == 'active-low')
- deasserted = (cs == 1) if active_low else (cs == 0)
- if deasserted:
- self.cs_was_deasserted = True
+ self.ss_block = self.samplenum
+ self.cs_was_deasserted = \
+ not self.cs_asserted(cs) if self.have_cs else False
- self.put(self.startsample, self.samplenum, self.out_bitrate, bitrate)
+ self.put(self.ss_block, self.samplenum, self.out_bitrate, bitrate)
if self.have_cs and self.cs_was_deasserted:
self.putw([4, ['CS# was deasserted during this data word!']])
if self.have_cs and self.cs_was_deasserted:
self.putw([4, ['CS# was deasserted during this data word!']])
self.handle_bit(miso, mosi, clk, cs)
def decode(self, ss, es, data):
self.handle_bit(miso, mosi, clk, cs)
def decode(self, ss, es, data):
# Either MISO or MOSI can be omitted (but not both). CS# is optional.
for (self.samplenum, pins) in data:
# Either MISO or MOSI can be omitted (but not both). CS# is optional.
for (self.samplenum, pins) in data:
- # State machine.
- if self.state == 'IDLE':
- self.find_clk_edge(miso, mosi, clk, cs)
- else:
- raise Exception('Invalid state: %s' % self.state)
+ # Tell stacked decoders that we don't have a CS# signal.
+ if not self.no_cs_notification and not self.have_cs:
+ self.put(0, 0, self.out_python, ['CS-CHANGE', None, None])
+ self.no_cs_notification = True