- self.crc = t[5] >> 1
- self.put(0, 0, self.out_ann, [0, ['CRC: 0x%01x' % self.crc]])
-
- # End bit
- self.endbit = t[5] & (1 << 0)
- self.put(0, 0, self.out_ann, [0, ['End bit: %d' % self.endbit]])
- if self.endbit != 1:
+ crc = t[5] >> 1
+ self.bit_ss, self.bit_es = tb(0, 7)[1], tb(0, 1)[2]
+ self.putb([70, ['CRC: 0x%01x' % crc]])
+
+ # Bits[0:0]: End bit (always 1)
+ bit, self.bit_ss, self.bit_es = tb(0, 0)[0], tb(0, 0)[1], tb(0, 0)[2]
+ self.putb([70, ['End bit: %d' % bit]])
+ if bit != 1: