- self.put(self.miso_bits[3][1], self.miso_bits[1][2], self.out_ann, [134, ['Data accepted']])
- elif miso == 0x0B:
- self.put(self.miso_bits[3][1], self.miso_bits[1][2], self.out_ann, [134, ['Data rejected (CRC error)']])
- elif miso == 0x0D:
- self.put(self.miso_bits[3][1], self.miso_bits[1][2], self.out_ann, [134, ['Data rejected (write error)']])
- self.put(self.miso_bits[0][1], self.miso_bits[0][2], self.out_ann, [134, ['1']])
- self.put(self.ss, self.es, self.out_ann, [24, ['Data Response']]) # Assume cmd24 initiated the transfer.
- self.state = 'IDLE'
+ self.put(m[3][1], m[1][2], self.out_ann, [Ann.BIT, ['Data accepted']])
+ elif miso == 0x0b:
+ self.put(m[3][1], m[1][2], self.out_ann, [Ann.BIT, ['Data rejected (CRC error)']])
+ elif miso == 0x0d:
+ self.put(m[3][1], m[1][2], self.out_ann, [Ann.BIT, ['Data rejected (write error)']])
+ self.put(m[0][1], m[0][2], self.out_ann, [Ann.BIT, ['Always 1']])
+ cls = Ann.CMD24 if self.is_cmd24 else None
+ if cls is not None:
+ self.put(self.ss, self.es, self.out_ann, [cls, ['Data Response']])
+ if self.is_cmd24:
+ # We just send a block of data to be written to the card,
+ # this takes some time.
+ self.state = 'WAIT WHILE CARD BUSY'
+ self.busy_first_byte = True
+ else:
+ self.state = 'IDLE'
+
+ def wait_while_busy(self, miso):
+ if miso != 0x00:
+ cls = Ann.CMD24 if self.is_cmd24 else None
+ if cls is not None:
+ self.put(self.ss_busy, self.es_busy, self.out_ann, [cls, ['Card is busy']])
+ self.state = 'IDLE'
+ return
+ else:
+ if self.busy_first_byte:
+ self.ss_busy = self.ss
+ self.busy_first_byte = False
+ else:
+ self.es_busy = self.es