- def find_clk_edge(self, clk, datapins):
- # Ignore sample if the clock pin hasn't changed.
- if clk == self.oldclk:
- return
- self.oldclk = clk
-
- # Sample data on rising/falling clock edge (depends on config).
- c = self.options['clock_edge']
- if c == 'rising' and clk == 0: # Sample on rising clock edge.
- return
- elif c == 'falling' and clk == 1: # Sample on falling clock edge.
- return
-
- # Found the correct clock edge, now get the bits.
- self.handle_bits(datapins)
-
- def decode(self, ss, es, data):
- for (self.samplenum, pins) in data:
-
- # Ignore identical samples early on (for performance reasons).
- if self.oldpins == pins:
- continue
- self.oldpins = pins
-
- # State machine.
- if self.state == 'IDLE':
- if pins[0] not in (0, 1):
- self.handle_bits(pins[1:])
- else:
- self.find_clk_edge(pins[0], pins[1:])
- else:
- raise Exception('Invalid state: %s' % self.state)
-
+ def decode(self):
+ for i in range(len(self.optional_channels)):
+ if self.has_channel(i):
+ self.num_channels += 1
+
+ if self.num_channels == 0:
+ raise ChannelError('At least one channel has to be supplied.')
+
+ if not self.has_channel(0):
+ # CLK was not supplied, sample on ANY edge of ANY of the pins
+ # (but only of those pins that were actually supplied).
+ conds = []
+ for i in range(1, len(self.optional_channels)):
+ if self.has_channel(i):
+ conds.append({i: 'e'})
+ while True:
+ self.handle_bits(self.wait(conds)[1:])
+ else:
+ # Sample on the rising or falling CLK edge (depends on config).
+ while True:
+ pins = self.wait({0: self.options['clock_edge'][0]})
+ self.handle_bits(pins[1:])