- # Go to waiting for sample time.
- self.state = 'WAIT FOR DATA SAMPLE'
- elif self.state == 'WAIT FOR DATA SAMPLE':
- # Sample data bit.
- t = self.samplenum - self.fall
- if t == self.cnt_bit[self.overdrive]:
- self.bit = owr
- self.state = 'WAIT FOR DATA SLOT END'
- elif self.state == 'WAIT FOR DATA SLOT END':
- # A data slot ends in a recovery period, otherwise, this is
- # probably a reset.
- t = self.samplenum - self.fall
- if t != self.cnt_slot[self.overdrive]:
- continue
-
- if owr == 0:
- # This seems to be a reset slot, wait for its end.
- self.state = 'WAIT FOR RISING EDGE'
- continue
-
- self.putb([0, ['Bit: %d' % self.bit]])
- self.putpb(['BIT', self.bit])
+ # Get time since last rising edge.
+ time = ((self.fall - self.rise) / self.samplerate) * 1000000.0
+ if self.rise > 0 and \
+ time < timing['REC']['min'][self.overdrive]:
+ self.putfr([1, ['Recovery time not long enough'
+ 'Recovery too short',
+ 'REC < ' + str(timing['REC']['min'][self.overdrive])]])
+ # A reset pulse or slot can start on a falling edge.
+ self.state = 'LOW'
+ # TODO: Check minimum recovery time.
+ elif self.state == 'LOW': # Reset pulse or slot.
+ # Wait for rising edge.
+ self.wait({0: 'r'})
+ self.rise = self.samplenum
+ # Detect reset or slot base on timing.
+ time = ((self.rise - self.fall) / self.samplerate) * 1000000.0
+ if time >= timing['RSTL']['min'][False]: # Normal reset pulse.
+ if time > timing['RSTL']['max'][False]:
+ self.putfr([1, ['Too long reset pulse might mask interrupt ' +
+ 'signalling by other devices',
+ 'Reset pulse too long',
+ 'RST > ' + str(timing['RSTL']['max'][False])]])
+ # Regular reset pulse clears overdrive speed.
+ if self.overdrive:
+ self.putfr([4, ['Exiting overdrive mode', 'Overdrive off']])
+ self.overdrive = False
+ self.putfr([2, ['Reset', 'Rst', 'R']])
+ self.state = 'PRESENCE DETECT HIGH'
+ elif self.overdrive == True and \
+ time >= timing['RSTL']['min'][self.overdrive] and \
+ time < timing['RSTL']['max'][self.overdrive]:
+ # Overdrive reset pulse.
+ self.putfr([2, ['Reset', 'Rst', 'R']])
+ self.state = 'PRESENCE DETECT HIGH'
+ elif time < timing['SLOT']['max'][self.overdrive]:
+ # Read/write time slot.
+ if time < timing['LOWR']['min'][self.overdrive]:
+ self.putfr([1, ['Low signal not long enough',
+ 'Low too short',
+ 'LOW < ' + str(timing['LOWR']['min'][self.overdrive])]])
+ if time < timing['LOWR']['max'][self.overdrive]:
+ self.bit = 1 # Short pulse is a 1 bit.
+ else:
+ self.bit = 0 # Long pulse is a 0 bit.
+ # Wait for end of slot.
+ self.state = 'SLOT'
+ else:
+ # Timing outside of known states.
+ self.putfr([1, ['Erroneous signal', 'Error', 'Err', 'E']])
+ self.state = 'IDLE'
+ elif self.state == 'PRESENCE DETECT HIGH': # Wait for slave presence signal.
+ # Wait for a falling edge and/or presence detect signal.
+ self.wait_falling_timeout(self.rise, timing['PDH']['max'])