+# TODO: Split off generic ARM/Cortex-M3 parts into another protocol decoder?
+
+# Bits[31:28]: Version (here: 0x3)
+# JTAG-DP: 0x3, SW-DP: 0x2
+# Bits[27:12]: Part number (here: 0xba00)
+# JTAG-DP: 0xba00, SW-DP: 0xba10
+# Bits[11:1]: JEDEC (JEP-106) manufacturer ID (here: 0x23b)
+# Bits[11:8]: Continuation code ('ARM Limited': 0x04)
+# Bits[7:1]: Identity code ('ARM Limited': 0x3b)
+# Bits[0:0]: Reserved (here: 0x1)
+def decode_device_id_code(bits):
+ id_hex = '0x%x' % int('0b' + bits, 2)
+ ver = '0x%x' % int('0b' + bits[-32:-28], 2)
+ part = '0x%x' % int('0b' + bits[-28:-12], 2)
+ manuf = '0x%x' % int('0b' + bits[-12:-1], 2)
+ res = '0x%x' % int('0b' + bits[-1], 2)
+ return (id_hex, ver, part, manuf, res)
+
+# DPACC is used to access debug port registers (CTRL/STAT, SELECT, RDBUFF).
+# APACC is used to access all Access Port (AHB-AP) registers.
+
+# APACC/DPACC, when transferring data IN:
+# Bits[34:3] = DATA[31:0]: 32bit data to transfer (write request)
+# Bits[2:1] = A[3:2]: 2-bit address (debug/access port register)
+# Bits[0:0] = RnW: Read request (1) or write request (0)
+def data_in(instruction, bits):
+ data, a, rnw = bits[:-3], bits[-3:-1], bits[-1]
+ data_hex = '0x%x' % int('0b' + data, 2)
+ r = 'Read request' if (rnw == '1') else 'Write request'
+ # reg = dp_reg[a] if (instruction == 'DPACC') else apb_ap_reg[a]
+ reg = dp_reg[a] if (instruction == 'DPACC') else a # TODO
+ return 'New transaction: DATA: %s, A: %s, RnW: %s' % (data_hex, reg, r)
+
+# APACC/DPACC, when transferring data OUT:
+# Bits[34:3] = DATA[31:0]: 32bit data which is read (read request)
+# Bits[2:0] = ACK[2:0]: 3-bit acknowledge
+def data_out(bits):
+ data, ack = bits[:-3], bits[-3:]
+ data_hex = '0x%x' % int('0b' + data, 2)
+ ack_meaning = ack_val.get(ack, 'Reserved')
+ return 'Previous transaction result: DATA: %s, ACK: %s' \
+ % (data_hex, ack_meaning)