+ ss_byte, es_byte = self.data_bits[0][1], self.data_bits[-1][2]
+
+ # Reverse the list of bits to LSB first order before emitting
+ # annotations and passing bits to upper layers. This may be
+ # unexpected because the protocol is MSB first, but it keeps
+ # backwards compatibility.
+ lsb_bits = self.data_bits[:]
+ lsb_bits.reverse()
+ self.putp(ss_byte, es_byte, ['BITS', lsb_bits])
+ self.putp(ss_byte, es_byte, [cmd, d])
+
+ self.putb(ss_byte, es_byte, [bin_class, bytes([d])])
+
+ for bit_value, ss_bit, es_bit in lsb_bits:
+ cls, texts = proto['BIT'][0], proto['BIT'][1:]
+ texts = [t.format(b = bit_value) for t in texts]
+ self.putg(ss_bit, es_bit, cls, texts)
+
+ if cmd.startswith('ADDRESS') and is_seven:
+ # Assign the last bit's location to the R/W annotation.
+ # Adjust the address value's location to the left.
+ ss_bit, es_bit = self.data_bits[-1][1], self.data_bits[-1][2]
+ es_byte = self.data_bits[-2][2]
+ cls = proto[cmd][0]
+ w = ['Write', 'Wr', 'W'] if self.is_write else ['Read', 'Rd', 'R']
+ self.putg(ss_bit, es_bit, cls, w)
+
+ cls, texts = proto[cmd][0], proto[cmd][1:]
+ texts = [t.format(b = d) for t in texts]
+ self.putg(ss_byte, es_byte, cls, texts)