- ('reg', 'Registers', (0, 1, 2, 3)),
- ('data', 'Data', (4, 5)),
+ ('reg', 'Registers', (Ann.READ, Ann.WRITE, Ann.MB, Ann.REG_ADDRESS)),
+ ('data', 'Data', (Ann.REG_DATA, Ann.WARNING)),
def handle_reg_with_scaling_factor(self, data, factor, name, unit, error_msg):
if data == 0 and error_msg is not None:
def handle_reg_with_scaling_factor(self, data, factor, name, unit, error_msg):
if data == 0 and error_msg is not None:
- self.putx([4, ['%s: %f %s' % (name, result, unit), '%f %s' % (result, unit)]])
+ self.putx([Ann.REG_DATA, ['%s: %f %s' % (name, result, unit), '%f %s' % (result, unit)]])
def handle_reg_bit_msg(self, bit, index, en_msg, dis_msg):
def handle_reg_bit_msg(self, bit, index, en_msg, dis_msg):
data <<= 8
self.data |= data
self.put(self.start_index, self.es, self.out_ann,
data <<= 8
self.data |= data
self.put(self.start_index, self.es, self.out_ann,
- [4, ['%s: 0x%04X' % (axis, self.data), str(data)]])
+ [Ann.REG_DATA, ['%s: 0x%04X' % (axis, self.data), str(data)]])
self.handle_reg_with_scaling_factor(data, 62.5, 'Threshold', 'g',
error_messages['undesirable'])
self.handle_reg_with_scaling_factor(data, 62.5, 'Threshold', 'g',
error_messages['undesirable'])
self.handle_reg_with_scaling_factor(data, 15.6, 'OFSX', 'g', None)
self.handle_reg_with_scaling_factor(data, 15.6, 'OFSX', 'g', None)
self.handle_reg_with_scaling_factor(data, 15.6, 'OFSY', 'g', None)
def handle_reg_0x20(self, data):
self.handle_reg_with_scaling_factor(data, 15.6, 'OFSZ', 'g', None)
def handle_reg_0x21(self, data):
self.handle_reg_with_scaling_factor(data, 15.6, 'OFSY', 'g', None)
def handle_reg_0x20(self, data):
self.handle_reg_with_scaling_factor(data, 15.6, 'OFSZ', 'g', None)
def handle_reg_0x21(self, data):
- self.handle_reg_with_scaling_factor(data, 0.625, 'Time', 's',
+ self.handle_reg_with_scaling_factor(data, 0.625, 'Duration', 's',
error_messages['dis_single_double'])
def handle_reg_0x22(self, data):
error_messages['dis_single_double'])
def handle_reg_0x22(self, data):
- self.handle_reg_with_scaling_factor(data, 62.5, 'Latent', 's',
+ self.handle_reg_with_scaling_factor(data, 1.25, 'Latency', 's',
error_messages['dis_double'])
def handle_reg_0x23(self, data):
error_messages['dis_double'])
def handle_reg_0x23(self, data):
- self.handle_reg_with_scaling_factor(data, 1.25, 'Latent', 's',
+ self.handle_reg_with_scaling_factor(data, 1.25, 'Window', 's',
error_messages['dis_double'])
def handle_reg_0x24(self, data):
error_messages['dis_double'])
def handle_reg_0x24(self, data):
- self.handle_reg_with_scaling_factor(data, 62.5, 'Latent', 's',
- error_messages['undesirable'])
+ self.handle_reg_0x1d(data)
def handle_reg_0x26(self, data):
self.handle_reg_with_scaling_factor(data, 1000, 'Time', 's',
def handle_reg_0x26(self, data):
self.handle_reg_with_scaling_factor(data, 1000, 'Time', 's',
self.interpret_bits(data, bits)
def handle_reg_0x28(self, data):
self.interpret_bits(data, bits)
def handle_reg_0x28(self, data):
def handle_reg_0x29(self, data):
self.handle_reg_with_scaling_factor(data, 5, 'Time', 's',
error_messages['undesirable'])
def handle_reg_0x29(self, data):
self.handle_reg_with_scaling_factor(data, 5, 'Time', 's',
error_messages['undesirable'])
Bit('TAP_Z', BitType.ENABLE)]
self.interpret_bits(data, bits)
Bit('TAP_Z', BitType.ENABLE)]
self.interpret_bits(data, bits)
bits = [Bit('', BitType.UNUSED),
Bit('ACT_X', BitType.SOURCE),
Bit('ACT_Y', BitType.SOURCE),
bits = [Bit('', BitType.UNUSED),
Bit('ACT_X', BitType.SOURCE),
Bit('ACT_Y', BitType.SOURCE),
Bit('TAP_Z', BitType.SOURCE)]
self.interpret_bits(data, bits)
Bit('TAP_Z', BitType.SOURCE)]
self.interpret_bits(data, bits)
bits_values = self.interpret_bits(data, bits)
start_index, stop_index = 0, 3
bits_values = self.interpret_bits(data, bits)
start_index, stop_index = 0, 3
- rate = self.get_decimal_number(bits_values, start_index, start_index)
- self.putbs([4, ['%f' % rate_code[rate]]], stop_index, start_index)
+ rate = self.get_decimal_number(bits_values, start_index, stop_index)
+ self.putbs([Ann.REG_DATA, ['%f' % rate_code[rate]]], stop_index, start_index)
bits = [Bit('', BitType.UNUSED),
Bit('', BitType.UNUSED),
Bit('', BitType.OTHER, {1: ['Link'], 0: ['Unlink'], }),
bits = [Bit('', BitType.UNUSED),
Bit('', BitType.UNUSED),
Bit('', BitType.OTHER, {1: ['Link'], 0: ['Unlink'], }),
start_index, stop_index = 0, 1
wakeup = self.get_decimal_number(bits_values, start_index, stop_index)
frequency = 2 ** (~wakeup & 0x03)
start_index, stop_index = 0, 1
wakeup = self.get_decimal_number(bits_values, start_index, stop_index)
frequency = 2 ** (~wakeup & 0x03)
- self.putbs([4, ['%d Hz' % frequency]], stop_index, start_index)
+ self.putbs([Ann.REG_DATA, ['%d Hz' % frequency]], stop_index, start_index)
bits = [Bit('DATA_READY', BitType.ENABLE),
Bit('SINGLE_TAP', BitType.ENABLE),
Bit('DOUBLE_TAP', BitType.ENABLE),
bits = [Bit('DATA_READY', BitType.ENABLE),
Bit('SINGLE_TAP', BitType.ENABLE),
Bit('DOUBLE_TAP', BitType.ENABLE),
Bit('Overrun', BitType.ENABLE)]
self.interpret_bits(data, bits)
Bit('Overrun', BitType.ENABLE)]
self.interpret_bits(data, bits)
bits = [Bit('DATA_READY', BitType.INTERRUPT),
Bit('SINGLE_TAP', BitType.INTERRUPT),
Bit('DOUBLE_TAP', BitType.INTERRUPT),
bits = [Bit('DATA_READY', BitType.INTERRUPT),
Bit('SINGLE_TAP', BitType.INTERRUPT),
Bit('DOUBLE_TAP', BitType.INTERRUPT),
start_index, stop_index = 0, 1
range_g = self.get_decimal_number(bits_values, start_index, stop_index)
result = 2 ** (range_g + 1)
start_index, stop_index = 0, 1
range_g = self.get_decimal_number(bits_values, start_index, stop_index)
result = 2 ** (range_g + 1)
- self.putbs([4, ['+/-%d g' % result]], stop_index, start_index)
+ self.putbs([Ann.REG_DATA, ['+/-%d g' % result]], stop_index, start_index)
def handle_reg_0x33(self, data):
self.get_axis_value(data, 'X')
def handle_reg_0x33(self, data):
self.get_axis_value(data, 'X')
start_index, stop_index = 6, 7
fifo = self.get_decimal_number(bits_values, start_index, stop_index)
start_index, stop_index = 6, 7
fifo = self.get_decimal_number(bits_values, start_index, stop_index)
- self.putbs([4, [fifo_modes[fifo]]], stop_index, start_index)
+ self.putbs([Ann.REG_DATA, [fifo_modes[fifo]]], stop_index, start_index)
start_index, stop_index = 0, 4
samples = self.get_decimal_number(bits_values, start_index, stop_index)
start_index, stop_index = 0, 4
samples = self.get_decimal_number(bits_values, start_index, stop_index)
- self.putbs([4, ['Samples: %d' % samples, '%d' % samples]], stop_index, start_index)
+ self.putbs([Ann.REG_DATA, ['Samples: %d' % samples, '%d' % samples]], stop_index, start_index)
def handle_reg_0x39(self, data):
bits = [Bit('', BitType.OTHER, {1: ['Triggered', 'Trigg'], 0: ['Not triggered', 'Not trigg'],}),
def handle_reg_0x39(self, data):
bits = [Bit('', BitType.OTHER, {1: ['Triggered', 'Trigg'], 0: ['Not triggered', 'Not trigg'],}),
start_index, stop_index = 0, 5
entries = self.get_decimal_number(bits_values, start_index, stop_index)
start_index, stop_index = 0, 5
entries = self.get_decimal_number(bits_values, start_index, stop_index)
- self.putbs([4, ['Entries: %d' % entries, '%d' % entries]], stop_index, start_index)
+ self.putbs([Ann.REG_DATA, ['Entries: %d' % entries, '%d' % entries]], stop_index, start_index)
def get_bit(self, channel):
if (channel == Channel.MOSI and self.mosi is None) or \
def get_bit(self, channel):
if (channel == Channel.MOSI and self.mosi is None) or \
cs_old, cs_new = data[1:]
if cs_old is not None and cs_old == 1 and cs_new == 0:
self.ss, self.es = ss, es
cs_old, cs_new = data[1:]
if cs_old is not None and cs_old == 1 and cs_new == 0:
self.ss, self.es = ss, es
# OPERATION BIT
op_bit = self.get_bit(Channel.MOSI)
self.put(op_bit[1], op_bit[2], self.out_ann,
# OPERATION BIT
op_bit = self.get_bit(Channel.MOSI)
self.put(op_bit[1], op_bit[2], self.out_ann,
self.operation = Operation.READ if op_bit[0] else Operation.WRITE
# MULTIPLE-BYTE BIT
mb_bit = self.get_bit(Channel.MOSI)
self.operation = Operation.READ if op_bit[0] else Operation.WRITE
# MULTIPLE-BYTE BIT
mb_bit = self.get_bit(Channel.MOSI)
- self.put(mb_bit[1], mb_bit[2], self.out_ann, [2, number_bytes[mb_bit[0]]])
+ self.put(mb_bit[1], mb_bit[2], self.out_ann, [Ann.MB, number_bytes[mb_bit[0]]])
self.address <<= 1
self.address >>= 1
self.put(start_sample, addr_bit[2], self.out_ann,
self.address <<= 1
self.address >>= 1
self.put(start_sample, addr_bit[2], self.out_ann,
self.reg.extend(self.mosi if self.operation == Operation.WRITE else self.miso)
self.mosi, self.miso = [], []
self.reg.extend(self.mosi if self.operation == Operation.WRITE else self.miso)
self.mosi, self.miso = [], []
- self.put(self.ss, reg_bit[2], self.out_ann, [3, [str(self.address)]])
- self.put(self.ss, reg_bit[2], self.out_ann, [4, [str(reg_value)]])
+ self.put(self.ss, reg_bit[2], self.out_ann, [Ann.REG_ADDRESS, [str(self.address)]])
+ self.put(self.ss, reg_bit[2], self.out_ann, [Ann.REG_DATA, [str(reg_value)]])
- self.put(self.ss, reg_bit[2], self.out_ann, [3, registers[self.address]])
- handle_reg = getattr(self, 'handle_reg_0x%02X' % self.address)
+ self.put(self.ss, reg_bit[2], self.out_ann, [Ann.REG_ADDRESS, registers[self.address]])
+ handle_reg = getattr(self, 'handle_reg_0x%02x' % self.address)