regvals = devc->reg_write_seq;
- regvals[0].reg = REG_CMD_CTRL2;
+ regvals[0].reg = REG_LONG_ADDR;
regvals[0].val = 10;
- regvals[1].reg = REG_CMD_CTRL3;
+ regvals[1].reg = REG_LONG_LOW;
regvals[1].val = 0;
- regvals[2].reg = REG_CMD_CTRL4;
+ regvals[2].reg = REG_LONG_HIGH;
regvals[2].val = 0;
- regvals[3].reg = REG_CMD_CTRL1;
+ regvals[3].reg = REG_LONG_STROBE;
regvals[3].val = 0;
regvals[4].reg = REG_DIV_BYPASS;
if (ret != SR_OK)
return ret;
- ret = lwla_write_reg(sdi->conn, REG_CMD_CTRL2, 100);
+ ret = lwla_write_reg(sdi->conn, REG_LONG_ADDR, 100);
if (ret != SR_OK)
return ret;
- ret = lwla_read_reg(sdi->conn, REG_CMD_CTRL1, &value);
+ ret = lwla_read_reg(sdi->conn, REG_LONG_STROBE, &value);
if (ret != SR_OK)
return ret;
sr_dbg("Received test word 0x%08X back.", value);
if (value != 0x12345678)
return SR_ERR;
- ret = lwla_read_reg(sdi->conn, REG_CMD_CTRL4, &value);
+ ret = lwla_read_reg(sdi->conn, REG_LONG_HIGH, &value);
if (ret != SR_OK)
return ret;
sr_dbg("Received test word 0x%08X back.", value);
if (value != 0x12345678)
return SR_ERR;
- ret = lwla_read_reg(sdi->conn, REG_CMD_CTRL3, &value);
+ ret = lwla_read_reg(sdi->conn, REG_LONG_LOW, &value);
if (ret != SR_OK)
return ret;
sr_dbg("Received test word 0x%08X back.", value);
SR_PRIV int lwla_set_clock_config(const struct sr_dev_inst *sdi)
{
struct dev_context *devc;
+ struct drv_context *drvc;
int ret;
enum clock_config choice;
devc = sdi->priv;
+ drvc = sdi->driver->context;
if (sdi->status == SR_ST_INACTIVE)
choice = CONF_CLOCK_NONE;
if (choice != devc->cur_clock_config) {
devc->cur_clock_config = CONF_CLOCK_NONE;
- ret = lwla_send_bitstream(sdi->conn, bitstream_map[choice]);
+ ret = lwla_send_bitstream(drvc->sr_ctx, sdi->conn,
+ bitstream_map[choice]);
if (ret == SR_OK)
devc->cur_clock_config = choice;
return ret;
regvals[1].reg = REG_MEM_CTRL2;
regvals[1].val = 1;
- regvals[2].reg = REG_CMD_CTRL2;
+ regvals[2].reg = REG_LONG_ADDR;
regvals[2].val = 10;
- regvals[3].reg = REG_CMD_CTRL3;
+ regvals[3].reg = REG_LONG_LOW;
regvals[3].val = 0x74;
- regvals[4].reg = REG_CMD_CTRL4;
+ regvals[4].reg = REG_LONG_HIGH;
regvals[4].val = 0;
- regvals[5].reg = REG_CMD_CTRL1;
+ regvals[5].reg = REG_LONG_STROBE;
regvals[5].val = 0;
regvals[6].reg = REG_DIV_BYPASS;
regvals = devc->reg_write_seq;
- regvals[0].reg = REG_CMD_CTRL2;
+ regvals[0].reg = REG_LONG_ADDR;
regvals[0].val = 10;
- regvals[1].reg = REG_CMD_CTRL3;
+ regvals[1].reg = REG_LONG_LOW;
regvals[1].val = 1;
- regvals[2].reg = REG_CMD_CTRL4;
+ regvals[2].reg = REG_LONG_HIGH;
regvals[2].val = 0;
- regvals[3].reg = REG_CMD_CTRL1;
+ regvals[3].reg = REG_LONG_STROBE;
regvals[3].val = 0;
devc->reg_write_pos = 0;