uint64_t sample, high_nibbles, word;
uint32_t *slice;
uint8_t *out_p;
- unsigned int words_left;
- unsigned int max_samples, run_samples;
- unsigned int wi, ri, si;
+ unsigned int words_left, max_samples, run_samples, wi, ri, si;
/* Number of 36-bit words remaining in the transfer buffer. */
words_left = MIN(acq->mem_addr_next, acq->mem_addr_stop)
acq->samples_done += run_samples;
if (run_samples == max_samples)
- break; /* packet full or sample limit reached */
+ break; /* Packet full or sample limit reached. */
if (wi >= words_left)
- break; /* done with current transfer */
+ break; /* Done with current transfer. */
/* Get the current slice of 8 packed 36-bit words. */
slice = &acq->xfer_buf_in[(acq->in_index + wi) / 8 * 9];
- si = (acq->in_index + wi) % 8; /* word index within slice */
+ si = (acq->in_index + wi) % 8; /* Word index within slice. */
/* Extract the next 36-bit word. */
high_nibbles = LWLA_TO_UINT32(slice[8]);
acq->rle = RLE_STATE_DATA;
}
}
+
acq->in_index += wi;
acq->mem_addr_done += wi;
}
{
struct dev_context *devc;
struct sr_usb_dev_inst *usb;
- int xfer_len;
- int ret;
+ int xfer_len, ret;
uint16_t command[3];
unsigned char buf[512];
-
const int lreg_count = 10;
devc = sdi->priv;
- usb = sdi->conn;
+ usb = sdi->conn;
command[0] = LWLA_WORD(CMD_READ_LREGS);
command[1] = LWLA_WORD(0);
{
struct dev_context *devc;
struct drv_context *drvc;
- int config;
- int ret;
+ int config, ret;
devc = sdi->priv;
drvc = sdi->driver->context;
config = FPGA_EXTNEG;
if (config == devc->active_fpga_config)
- return SR_OK; /* no change */
+ return SR_OK; /* No change. */
ret = lwla_send_bitstream(drvc->sr_ctx, sdi->conn,
bitstream_map[config]);
*/
static int setup_acquisition(const struct sr_dev_inst *sdi)
{
- uint64_t divider_count;
- uint64_t trigger_mask;
+ static const struct regval capture_init[] = {
+ {REG_MEM_CTRL, MEM_CTRL_CLR_IDX},
+ {REG_MEM_CTRL, MEM_CTRL_WRITE},
+ {REG_LONG_ADDR, LREG_CAP_CTRL},
+ {REG_LONG_LOW, CAP_CTRL_CLR_TIMEBASE | CAP_CTRL_FLUSH_FIFO |
+ CAP_CTRL_CLR_FIFOFULL | CAP_CTRL_CLR_COUNTER},
+ {REG_LONG_HIGH, 0},
+ {REG_LONG_STROBE, 0},
+ };
+ uint64_t divider_count, trigger_mask;
struct dev_context *devc;
struct sr_usb_dev_inst *usb;
struct acquisition_state *acq;
int ret;
devc = sdi->priv;
- usb = sdi->conn;
- acq = devc->acquisition;
-
- acq->reg_seq_pos = 0;
- acq->reg_seq_len = 0;
+ usb = sdi->conn;
+ acq = devc->acquisition;
- lwla_queue_regval(acq, REG_MEM_CTRL, MEM_CTRL_CLR_IDX);
- lwla_queue_regval(acq, REG_MEM_CTRL, MEM_CTRL_WRITE);
-
- queue_long_regval(acq, LREG_CAP_CTRL,
- CAP_CTRL_CLR_TIMEBASE | CAP_CTRL_FLUSH_FIFO |
- CAP_CTRL_CLR_FIFOFULL | CAP_CTRL_CLR_COUNTER);
-
- lwla_queue_regval(acq, REG_CLK_BOOST, acq->clock_boost);
-
- ret = lwla_write_regs(usb, acq->reg_sequence, acq->reg_seq_len);
- acq->reg_seq_len = 0;
+ ret = lwla_write_regs(usb, capture_init, ARRAY_SIZE(capture_init));
+ if (ret != SR_OK)
+ return ret;
+ ret = lwla_write_reg(usb, REG_CLK_BOOST, acq->clock_boost);
if (ret != SR_OK)
return ret;
bulk_long_set(acq, LREG_DIV_COUNT, divider_count);
bulk_long_set(acq, LREG_TRG_VALUE, devc->trigger_values);
- bulk_long_set(acq, LREG_TRG_TYPE, devc->trigger_edge_mask);
+ bulk_long_set(acq, LREG_TRG_TYPE, devc->trigger_edge_mask);
trigger_mask = devc->trigger_mask;
int expect_len;
devc = sdi->priv;
- acq = devc->acquisition;
+ acq = devc->acquisition;
switch (devc->state) {
case STATE_STATUS_REQUEST:
return SR_ERR;
}
acq->mem_addr_fill = bulk_long_get(acq, LREG_MEM_FILL) & 0xFFFFFFFF;
- acq->duration_now = bulk_long_get(acq, LREG_DURATION);
+ acq->duration_now = bulk_long_get(acq, LREG_DURATION);
/* Shift left by one so the bit positions match the LWLA1016. */
acq->status = (bulk_long_get(acq, LREG_STATUS) & 0x3F) << 1;
/*