#define FPGA_FIRMWARE_33 "saleae-logic16-fpga-33.bitstream"
#define MAX_SAMPLE_RATE SR_MHZ(100)
-#define MAX_4CH_SAMPLE_RATE SR_MHZ(50)
-#define MAX_7CH_SAMPLE_RATE SR_MHZ(40)
-#define MAX_8CH_SAMPLE_RATE SR_MHZ(32)
-#define MAX_10CH_SAMPLE_RATE SR_MHZ(25)
-#define MAX_13CH_SAMPLE_RATE SR_MHZ(16)
+#define MAX_SAMPLE_RATE_X_CH SR_MHZ(300)
#define BASE_CLOCK_0_FREQ SR_MHZ(100)
#define BASE_CLOCK_1_FREQ SR_MHZ(160)
if (channels & (1U << i))
nchan++;
- if ((nchan >= 13 && samplerate > MAX_13CH_SAMPLE_RATE) ||
- (nchan >= 10 && samplerate > MAX_10CH_SAMPLE_RATE) ||
- (nchan >= 8 && samplerate > MAX_8CH_SAMPLE_RATE) ||
- (nchan >= 7 && samplerate > MAX_7CH_SAMPLE_RATE) ||
- (nchan >= 4 && samplerate > MAX_4CH_SAMPLE_RATE)) {
+ if (nchan * samplerate > MAX_SAMPLE_RATE_X_CH) {
sr_err("Unable to sample at %" PRIu64 "Hz "
"with this many channels.", samplerate);
return SR_ERR;
devc = sdi->priv;
- std_session_send_df_end(sdi, LOG_PREFIX);
+ std_session_send_df_end(sdi);
- /* Remove fds from polling. */
usb_source_remove(sdi->session, devc->ctx);
devc->num_transfers = 0;
new_samples = convert_sample_data(devc, devc->convbuffer,
devc->convbuffer_size, transfer->buffer, transfer->actual_length);
- if (new_samples > 0) {
- if (devc->trigger_fired) {
- /* Send the incoming transfer to the session bus. */
+ if (new_samples <= 0) {
+ resubmit_transfer(transfer);
+ return;
+ }
+
+ /* At least one new sample. */
+ if (devc->trigger_fired) {
+ /* Send the incoming transfer to the session bus. */
+ packet.type = SR_DF_LOGIC;
+ packet.payload = &logic;
+ if (devc->limit_samples &&
+ new_samples > devc->limit_samples - devc->sent_samples)
+ new_samples = devc->limit_samples - devc->sent_samples;
+ logic.length = new_samples * 2;
+ logic.unitsize = 2;
+ logic.data = devc->convbuffer;
+ sr_session_send(sdi, &packet);
+ devc->sent_samples += new_samples;
+ } else {
+ trigger_offset = soft_trigger_logic_check(devc->stl,
+ devc->convbuffer, new_samples * 2, &pre_trigger_samples);
+ if (trigger_offset > -1) {
+ devc->sent_samples += pre_trigger_samples;
packet.type = SR_DF_LOGIC;
packet.payload = &logic;
+ num_samples = new_samples - trigger_offset;
if (devc->limit_samples &&
- new_samples > devc->limit_samples - devc->sent_samples)
- new_samples = devc->limit_samples - devc->sent_samples;
- logic.length = new_samples * 2;
+ num_samples > devc->limit_samples - devc->sent_samples)
+ num_samples = devc->limit_samples - devc->sent_samples;
+ logic.length = num_samples * 2;
logic.unitsize = 2;
- logic.data = devc->convbuffer;
+ logic.data = devc->convbuffer + trigger_offset * 2;
sr_session_send(sdi, &packet);
- devc->sent_samples += new_samples;
- } else {
- trigger_offset = soft_trigger_logic_check(devc->stl,
- devc->convbuffer, new_samples * 2, &pre_trigger_samples);
- if (trigger_offset > -1) {
- devc->sent_samples += pre_trigger_samples;
- packet.type = SR_DF_LOGIC;
- packet.payload = &logic;
- num_samples = new_samples - trigger_offset;
- if (devc->limit_samples &&
- num_samples > devc->limit_samples - devc->sent_samples)
- num_samples = devc->limit_samples - devc->sent_samples;
- logic.length = num_samples * 2;
- logic.unitsize = 2;
- logic.data = devc->convbuffer + trigger_offset * 2;
- sr_session_send(sdi, &packet);
- devc->sent_samples += num_samples;
-
- devc->trigger_fired = TRUE;
- }
- }
+ devc->sent_samples += num_samples;
- if (devc->limit_samples &&
- (uint64_t)devc->sent_samples >= devc->limit_samples) {
- devc->sent_samples = -2;
- free_transfer(transfer);
- return;
+ devc->trigger_fired = TRUE;
}
}
+ if (devc->limit_samples &&
+ (uint64_t)devc->sent_samples >= devc->limit_samples) {
+ devc->sent_samples = -2;
+ free_transfer(transfer);
+ return;
+ }
+
resubmit_transfer(transfer);
}