* The device expects some zero padding to follow the content of the
* file which contains the FPGA bitstream. Specify the chunk size here.
*/
-#define LA2016_EP2_PADDING 2048
+#define LA2016_EP2_PADDING 4096
/*
* Whether the logic input threshold voltage is a config item of the
#define LA2016_THR_VOLTAGE_MIN 0.40
#define LA2016_THR_VOLTAGE_MAX 4.00
-/* Properties related to the layout of capture data downloads. */
-#define TRANSFER_PACKET_LENGTH 16
#define LA2016_NUM_SAMPLES_MAX (UINT64_C(10 * 1000 * 1000 * 1000))
/* Maximum device capabilities. May differ between models. */
uint64_t samplerate; /* Max samplerate in Hz. */
size_t channel_count; /* Max channel count (16, 32). */
uint64_t memory_bits; /* RAM capacity in Gbit (1, 2, 4). */
+ uint64_t baseclock; /* Base clock to derive samplerate from. */
};
struct dev_context {
uint64_t fw_uploaded; /* Timestamp of most recent FW upload. */
uint8_t identify_magic, identify_magic2;
const struct kingst_model *model;
+ char **channel_names_logic;
struct sr_channel_group *cg_logic, *cg_pwm;
/* User specified parameters. */
gboolean frame_begin_sent;
gboolean completion_seen;
gboolean download_finished;
+ size_t transfer_size;
+ size_t sequence_size;
uint32_t packets_per_chunk;
struct capture_info {
uint32_t n_rep_packets;