L = len(cmds)
-# Don't forget to keep this in sync with 'cmds' is lists.py.
+# Don't forget to keep this in sync with 'cmds' in lists.py.
class Ann:
WRSR, PP, READ, WRDI, RDSR, WREN, FAST_READ, SE, RDSCUR, WRSCUR, \
RDSR2, CE, ESRY, DSRY, WRITE1, WRITE2, REMS, RDID, RDP_RES, CP, ENSO, DP, \
class Decoder(srd.Decoder):
api_version = 3
id = 'spiflash'
- name = 'SPI flash'
- longname = 'SPI flash chips'
- desc = 'xx25 series SPI (NOR) flash chip protocol.'
+ name = 'SPI flash/EEPROM'
+ longname = 'SPI flash/EEPROM chips'
+ desc = 'xx25 series SPI (NOR) flash/EEPROM chip protocol.'
license = 'gplv2+'
inputs = ['spi']
- outputs = ['spiflash']
+ outputs = []
+ tags = ['IC', 'Memory']
annotations = cmd_annotation_classes() + (
('bit', 'Bit'),
('field', 'Field'),
self.putx([Ann.BIT, [decode_status_reg(miso)]])
self.putx([Ann.FIELD, ['Status register']])
self.putc([Ann.RDSR, self.cmd_ann_list()])
+ # Set write latch state.
+ self.writestate = 1 if (miso & (1 << 1)) else 0
self.cmdstate += 1
def handle_rdsr2(self, mosi, miso):
# Byte 2: Master sends status register 1.
self.putx([Ann.BIT, [decode_status_reg(mosi)]])
self.putx([Ann.FIELD, ['Status register 1']])
+ # Set write latch state.
+ self.writestate = 1 if (miso & (1 << 1)) else 0
elif self.cmdstate == 3:
# Byte 3: Master sends status register 2.
# TODO: Decode status register 2 correctly.
self.putx([Ann.FIELD, ['%s ID: 0x%02x' % (d, miso)]])
if self.cmdstate == 6:
- id = self.ids[1] if self.manufacturer_id_first else self.ids[0]
- self.device_id = id
+ id_ = self.ids[1] if self.manufacturer_id_first else self.ids[0]
+ self.device_id = id_
self.es_cmd = self.es
self.putc([Ann.REMS, self.cmd_vendor_dev_list()])
self.state = None