## This file is part of the sigrok project.
##
## Copyright (C) 2011 Gareth McMullin <gareth@blacksphere.co.nz>
+## Copyright (C) 2012 Uwe Hermann <uwe@hermann-uwe.de>
##
## This program is free software; you can redistribute it and/or modify
## it under the terms of the GNU General Public License as published by
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
##
-import sigrokdecode
+import sigrokdecode as srd
-class Decoder(sigrokdecode.Decoder):
+# Annotation formats
+ANN_HEX = 0
+
+class Decoder(srd.Decoder):
id = 'spi'
name = 'SPI'
- desc = '...desc...'
longname = 'Serial Peripheral Interface (SPI) bus'
+ desc = '...desc...'
longdesc = '...longdesc...'
author = 'Gareth McMullin'
email = 'gareth@blacksphere.co.nz'
inputs = ['logic']
outputs = ['spi']
probes = [
- {'id': 'sdata', 'name': 'DATA', 'desc': 'SPI data line (MISO or MOSI)'},
+ {'id': 'mosi', 'name': 'MOSI',
+ 'desc': 'SPI MOSI line (Master out, slave in)'},
+ {'id': 'miso', 'name': 'MISO',
+ 'desc': 'SPI MISO line (Master in, slave out)'},
{'id': 'sck', 'name': 'CLK', 'desc': 'SPI clock line'},
+ {'id': 'cs', 'name': 'CS#', 'desc': 'SPI CS (chip select) line'},
]
options = {}
+ annotations = [
+ ['Hex', 'SPI data bytes in hex format'],
+ ]
def __init__(self):
self.oldsck = 1
- self.rxcount = 0
- self.rxdata = 0
+ self.bitcount = 0
+ self.mosidata = 0
+ self.misodata = 0
self.bytesreceived = 0
- self.out_proto = None
- self.out_ann = None
+ self.samplenum = -1
def start(self, metadata):
- # self.out_proto = self.add(sigrokdecode.SRD_OUTPUT_PROTOCOL, 'spi')
- self.out_ann = self.add(sigrokdecode.SRD_OUTPUT_ANNOTATION, 'spi')
+ self.out_proto = self.add(srd.OUTPUT_PROTO, 'spi')
+ self.out_ann = self.add(srd.OUTPUT_ANN, 'spi')
def report(self):
return 'SPI: %d bytes received' % self.bytesreceived
- def decode(self, timeoffset, duration, data):
+ def decode(self, ss, es, data):
# HACK! At the moment the number of probes is not handled correctly.
# E.g. if an input file (-i foo.sr) has more than two probes enabled.
- for (samplenum, (sdata, sck, x, y, z, a)) in data:
+ # for (samplenum, (mosi, sck, x, y, z, a)) in data:
+ # for (samplenum, (cs, miso, sck, mosi, wp, hold)) in data:
+ for (samplenum, (cs, miso, sck, mosi, wp, hold)) in data:
+
+ self.samplenum += 1 # FIXME
- # Sample SDATA on rising SCK
+ # Sample data on rising SCK edges.
if sck == self.oldsck:
continue
self.oldsck = sck
- if not sck:
+ if sck == 0:
continue
- # If this is first bit, save timestamp
- if self.rxcount == 0:
- self.time = timeoffset # FIXME
- # Receive bit into our shift register
- if sdata:
- self.rxdata |= 1 << (7 - self.rxcount)
- self.rxcount += 1
- # Continue to receive if not a byte yet
- if self.rxcount != 8:
+ # If this is the first bit, save its sample number.
+ if self.bitcount == 0:
+ self.start_sample = samplenum
+
+ # Receive bit into our shift register.
+ if mosi == 1:
+ self.mosidata |= 1 << (7 - self.bitcount)
+ if miso == 1:
+ self.misodata |= 1 << (7 - self.bitcount)
+
+ self.bitcount += 1
+
+ # Continue to receive if not a byte yet.
+ if self.bitcount != 8:
continue
- # Received a byte, pass up to sigrok
- outdata = {'time':self.time,
- 'duration':timeoffset + duration - self.time,
- 'data':self.rxdata,
- 'display':('%02X' % self.rxdata),
- 'type':'spi',
- }
- # self.put(0, 0, self.out_proto, out_proto)
- self.put(0, 0, self.out_ann, outdata)
- # Reset decoder state
- self.rxdata = 0
- self.rxcount = 0
- # Keep stats for summary
+
+ self.put(self.start_sample, self.samplenum, self.out_proto,
+ ['data', self.mosidata, self.misodata])
+ self.put(self.start_sample, self.samplenum, self.out_ann,
+ [ANN_HEX, ['MOSI: 0x%02x, MISO: 0x%02x' % (self.mosidata,
+ self.misodata)]])
+
+ # Reset decoder state.
+ self.mosidata = 0
+ self.misodata = 0
+ self.bitcount = 0
+
+ # Keep stats for summary.
self.bytesreceived += 1