2 * This file is part of the libsigrok project.
4 * Copyright (C) 2013 Marcus Comstedt <marcus@mc.pp.se>
5 * Copyright (C) 2013 Bert Vermeulen <bert@biot.com>
6 * Copyright (C) 2012 Joel Holdsworth <joel@airwebreathe.org.uk>
8 * This program is free software: you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation, either version 3 of the License, or
11 * (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program. If not, see <http://www.gnu.org/licenses/>.
27 #include <glib/gstdio.h>
31 #include "libsigrok.h"
32 #include "libsigrok-internal.h"
34 #define FPGA_FIRMWARE_18 FIRMWARE_DIR"/saleae-logic16-fpga-18.bitstream"
35 #define FPGA_FIRMWARE_33 FIRMWARE_DIR"/saleae-logic16-fpga-33.bitstream"
37 #define MAX_SAMPLE_RATE SR_MHZ(100)
38 #define MAX_4CH_SAMPLE_RATE SR_MHZ(50)
39 #define MAX_7CH_SAMPLE_RATE SR_MHZ(40)
40 #define MAX_8CH_SAMPLE_RATE SR_MHZ(32)
41 #define MAX_10CH_SAMPLE_RATE SR_MHZ(25)
42 #define MAX_13CH_SAMPLE_RATE SR_MHZ(16)
44 #define BASE_CLOCK_0_FREQ SR_MHZ(100)
45 #define BASE_CLOCK_1_FREQ SR_MHZ(160)
47 #define COMMAND_START_ACQUISITION 1
48 #define COMMAND_ABORT_ACQUISITION_ASYNC 2
49 #define COMMAND_WRITE_EEPROM 6
50 #define COMMAND_READ_EEPROM 7
51 #define COMMAND_WRITE_LED_TABLE 0x7a
52 #define COMMAND_SET_LED_MODE 0x7b
53 #define COMMAND_RETURN_TO_BOOTLOADER 0x7c
54 #define COMMAND_ABORT_ACQUISITION_SYNC 0x7d
55 #define COMMAND_FPGA_UPLOAD_INIT 0x7e
56 #define COMMAND_FPGA_UPLOAD_SEND_DATA 0x7f
57 #define COMMAND_FPGA_WRITE_REGISTER 0x80
58 #define COMMAND_FPGA_READ_REGISTER 0x81
59 #define COMMAND_GET_REVID 0x82
61 #define WRITE_EEPROM_COOKIE1 0x42
62 #define WRITE_EEPROM_COOKIE2 0x55
63 #define READ_EEPROM_COOKIE1 0x33
64 #define READ_EEPROM_COOKIE2 0x81
65 #define ABORT_ACQUISITION_SYNC_PATTERN 0x55
67 #define MAX_EMPTY_TRANSFERS 64
69 static void encrypt(uint8_t *dest, const uint8_t *src, uint8_t cnt)
71 uint8_t state1 = 0x9b, state2 = 0x54;
75 for (i = 0; i < cnt; i++) {
77 t = (((v ^ state2 ^ 0x2b) - 0x05) ^ 0x35) - 0x39;
78 t = (((t ^ state1 ^ 0x5a) - 0xb0) ^ 0x38) - 0x45;
84 static void decrypt(uint8_t *dest, const uint8_t *src, uint8_t cnt)
86 uint8_t state1 = 0x9b, state2 = 0x54;
90 for (i = 0; i < cnt; i++) {
92 t = (((v + 0x45) ^ 0x38) + 0xb0) ^ 0x5a ^ state1;
93 t = (((t + 0x39) ^ 0x35) + 0x05) ^ 0x2b ^ state2;
99 static int do_ep1_command(const struct sr_dev_inst *sdi,
100 const uint8_t *command, uint8_t cmd_len,
101 uint8_t *reply, uint8_t reply_len)
104 struct sr_usb_dev_inst *usb;
109 if (cmd_len < 1 || cmd_len > 64 || reply_len > 64 ||
110 command == NULL || (reply_len > 0 && reply == NULL))
113 encrypt(buf, command, cmd_len);
115 ret = libusb_bulk_transfer(usb->devhdl, 1, buf, cmd_len, &xfer, 1000);
117 sr_dbg("Failed to send EP1 command 0x%02x: %s.",
118 command[0], libusb_error_name(ret));
121 if (xfer != cmd_len) {
122 sr_dbg("Failed to send EP1 command 0x%02x: incorrect length "
123 "%d != %d.", xfer, cmd_len);
130 ret = libusb_bulk_transfer(usb->devhdl, 0x80 | 1, buf, reply_len,
133 sr_dbg("Failed to receive reply to EP1 command 0x%02x: %s.",
134 command[0], libusb_error_name(ret));
137 if (xfer != reply_len) {
138 sr_dbg("Failed to receive reply to EP1 command 0x%02x: "
139 "incorrect length %d != %d.", xfer, reply_len);
143 decrypt(reply, buf, reply_len);
148 static int read_eeprom(const struct sr_dev_inst *sdi,
149 uint8_t address, uint8_t length, uint8_t *buf)
151 uint8_t command[5] = {
159 return do_ep1_command(sdi, command, 5, buf, length);
162 static int upload_led_table(const struct sr_dev_inst *sdi,
163 const uint8_t *table, uint8_t offset, uint8_t cnt)
165 uint8_t chunk, command[64];
168 if (cnt < 1 || cnt + offset > 64 || table == NULL)
172 chunk = (cnt > 32 ? 32 : cnt);
174 command[0] = COMMAND_WRITE_LED_TABLE;
177 memcpy(command + 3, table, chunk);
179 ret = do_ep1_command(sdi, command, 3 + chunk, NULL, 0);
191 static int set_led_mode(const struct sr_dev_inst *sdi,
192 uint8_t animate, uint16_t t2reload, uint8_t div,
195 uint8_t command[6] = {
196 COMMAND_SET_LED_MODE,
204 return do_ep1_command(sdi, command, 6, NULL, 0);
207 static int read_fpga_register(const struct sr_dev_inst *sdi,
208 uint8_t address, uint8_t *value)
210 uint8_t command[3] = {
211 COMMAND_FPGA_READ_REGISTER,
216 return do_ep1_command(sdi, command, 3, value, 1);
219 static int write_fpga_registers(const struct sr_dev_inst *sdi,
220 uint8_t (*regs)[2], uint8_t cnt)
225 if (cnt < 1 || cnt > 31)
228 command[0] = COMMAND_FPGA_WRITE_REGISTER;
230 for (i = 0; i < cnt; i++) {
231 command[2 + 2 * i] = regs[i][0];
232 command[3 + 2 * i] = regs[i][1];
235 return do_ep1_command(sdi, command, 2 * (cnt + 1), NULL, 0);
238 static int write_fpga_register(const struct sr_dev_inst *sdi,
239 uint8_t address, uint8_t value)
241 uint8_t regs[2] = { address, value };
243 return write_fpga_registers(sdi, ®s, 1);
246 static uint8_t map_eeprom_data(uint8_t v)
248 return (((v ^ 0x80) + 0x44) ^ 0xd5) + 0x69;
251 static int prime_fpga(const struct sr_dev_inst *sdi)
253 uint8_t eeprom_data[16];
254 uint8_t old_reg_10, version;
255 uint8_t regs[8][2] = {
267 if ((ret = read_eeprom(sdi, 16, 16, eeprom_data)) != SR_OK)
270 if ((ret = read_fpga_register(sdi, 10, &old_reg_10)) != SR_OK)
273 regs[0][1] = (old_reg_10 &= 0x7f);
274 regs[1][1] |= old_reg_10;
275 regs[3][1] |= old_reg_10;
276 regs[4][1] |= old_reg_10;
278 for (i = 0; i < 16; i++) {
279 regs[2][1] = eeprom_data[i];
280 regs[5][1] = map_eeprom_data(eeprom_data[i]);
282 ret = write_fpga_registers(sdi, ®s[2], 6);
284 ret = write_fpga_registers(sdi, ®s[0], 8);
289 if ((ret = write_fpga_register(sdi, 10, old_reg_10)) != SR_OK)
292 if ((ret = read_fpga_register(sdi, 0, &version)) != SR_OK)
295 if (version != 0x10 && version != 0x40 && version != 0x41) {
296 sr_err("Unsupported FPGA version: 0x%02x.", version);
303 static void make_heartbeat(uint8_t *table, int len)
307 memset(table, 0, len);
309 for (i = 0; i < 2; i++)
310 for (j = 0; j < len; j++)
311 *table++ = sin(j * M_PI / len) * 255;
314 static int configure_led(const struct sr_dev_inst *sdi)
319 make_heartbeat(table, 64);
320 if ((ret = upload_led_table(sdi, table, 0, 64)) != SR_OK)
323 return set_led_mode(sdi, 1, 6250, 0, 1);
326 static int upload_fpga_bitstream(const struct sr_dev_inst *sdi,
327 enum voltage_range vrange)
329 struct dev_context *devc;
330 int offset, chunksize, ret;
331 const char *filename;
332 uint8_t len, buf[256 * 62], command[64];
337 if (devc->cur_voltage_range == vrange)
340 if (devc->fpga_variant == FPGA_VARIANT_ORIGINAL) {
342 case VOLTAGE_RANGE_18_33_V:
343 filename = FPGA_FIRMWARE_18;
345 case VOLTAGE_RANGE_5_V:
346 filename = FPGA_FIRMWARE_33;
349 sr_err("Unsupported voltage range.");
353 sr_info("Uploading FPGA bitstream at %s.", filename);
354 if ((fw = g_fopen(filename, "rb")) == NULL) {
355 sr_err("Unable to open bitstream file %s for reading: %s.",
356 filename, strerror(errno));
360 buf[0] = COMMAND_FPGA_UPLOAD_INIT;
361 if ((ret = do_ep1_command(sdi, buf, 1, NULL, 0)) != SR_OK) {
367 chunksize = fread(buf, 1, sizeof(buf), fw);
371 for (offset = 0; offset < chunksize; offset += 62) {
372 len = (offset + 62 > chunksize ?
373 chunksize - offset : 62);
374 command[0] = COMMAND_FPGA_UPLOAD_SEND_DATA;
376 memcpy(command + 2, buf + offset, len);
377 ret = do_ep1_command(sdi, command, len + 2, NULL, 0);
384 sr_info("Uploaded %d bytes.", chunksize);
387 sr_info("FPGA bitstream upload done.");
390 if ((ret = prime_fpga(sdi)) != SR_OK)
393 if ((ret = configure_led(sdi)) != SR_OK)
396 devc->cur_voltage_range = vrange;
400 static int abort_acquisition_sync(const struct sr_dev_inst *sdi)
402 static const uint8_t command[2] = {
403 COMMAND_ABORT_ACQUISITION_SYNC,
404 ABORT_ACQUISITION_SYNC_PATTERN,
406 uint8_t reply, expected_reply;
409 if ((ret = do_ep1_command(sdi, command, 2, &reply, 1)) != SR_OK)
412 expected_reply = ~command[1];
413 if (reply != expected_reply) {
414 sr_err("Invalid response for abort acquisition command: "
415 "0x%02x != 0x%02x.", reply, expected_reply);
422 SR_PRIV int logic16_setup_acquisition(const struct sr_dev_inst *sdi,
423 uint64_t samplerate, uint16_t channels)
425 uint8_t clock_select, reg1, reg10;
427 int i, ret, nchan = 0;
428 struct dev_context *devc;
432 if (samplerate == 0 || samplerate > MAX_SAMPLE_RATE) {
433 sr_err("Unable to sample at %" PRIu64 "Hz.", samplerate);
437 if (BASE_CLOCK_0_FREQ % samplerate == 0 &&
438 (div = BASE_CLOCK_0_FREQ / samplerate) <= 256) {
440 } else if (BASE_CLOCK_1_FREQ % samplerate == 0 &&
441 (div = BASE_CLOCK_1_FREQ / samplerate) <= 256) {
444 sr_err("Unable to sample at %" PRIu64 "Hz.", samplerate);
448 for (i = 0; i < 16; i++)
449 if (channels & (1U << i))
452 if ((nchan >= 13 && samplerate > MAX_13CH_SAMPLE_RATE) ||
453 (nchan >= 10 && samplerate > MAX_10CH_SAMPLE_RATE) ||
454 (nchan >= 8 && samplerate > MAX_8CH_SAMPLE_RATE) ||
455 (nchan >= 7 && samplerate > MAX_7CH_SAMPLE_RATE) ||
456 (nchan >= 4 && samplerate > MAX_4CH_SAMPLE_RATE)) {
457 sr_err("Unable to sample at %" PRIu64 "Hz "
458 "with this many channels.", samplerate);
462 ret = upload_fpga_bitstream(sdi, devc->selected_voltage_range);
466 if ((ret = read_fpga_register(sdi, 1, ®1)) != SR_OK)
469 /* Ignore FIFO overflow on previous capture */
472 if (devc->fpga_variant == FPGA_VARIANT_ORIGINAL && reg1 != 0x08) {
473 sr_dbg("Invalid state at acquisition setup register 1: 0x%02x != 0x08. "
474 "Proceeding anyway.", reg1);
477 if ((ret = write_fpga_register(sdi, 1, 0x40)) != SR_OK)
480 if ((ret = write_fpga_register(sdi, 10, clock_select)) != SR_OK)
483 if ((ret = write_fpga_register(sdi, 4, (uint8_t)(div - 1))) != SR_OK)
486 if ((ret = write_fpga_register(sdi, 2, (uint8_t)(channels & 0xff))) != SR_OK)
489 if ((ret = write_fpga_register(sdi, 3, (uint8_t)(channels >> 8))) != SR_OK)
492 if ((ret = write_fpga_register(sdi, 1, 0x42)) != SR_OK)
495 if ((ret = write_fpga_register(sdi, 1, 0x40)) != SR_OK)
498 if ((ret = read_fpga_register(sdi, 1, ®1)) != SR_OK)
501 if (devc->fpga_variant == FPGA_VARIANT_ORIGINAL && reg1 != 0x48) {
502 sr_dbg("Invalid state at acquisition setup register 1: 0x%02x != 0x48. "
503 "Proceeding anyway.", reg1);
506 if ((ret = read_fpga_register(sdi, 10, ®10)) != SR_OK)
509 if (devc->fpga_variant == FPGA_VARIANT_ORIGINAL && reg10 != clock_select) {
510 sr_dbg("Invalid state at acquisition setup register 10: 0x%02x != 0x%02x. "
511 "Proceeding anyway.", reg10, clock_select);
517 SR_PRIV int logic16_start_acquisition(const struct sr_dev_inst *sdi)
519 static const uint8_t command[1] = {
520 COMMAND_START_ACQUISITION,
524 if ((ret = do_ep1_command(sdi, command, 1, NULL, 0)) != SR_OK)
527 return write_fpga_register(sdi, 1, 0x41);
530 SR_PRIV int logic16_abort_acquisition(const struct sr_dev_inst *sdi)
532 static const uint8_t command[1] = {
533 COMMAND_ABORT_ACQUISITION_ASYNC,
536 uint8_t reg1, reg8, reg9;
537 struct dev_context *devc;
541 if ((ret = do_ep1_command(sdi, command, 1, NULL, 0)) != SR_OK)
544 if ((ret = write_fpga_register(sdi, 1, 0x00)) != SR_OK)
547 if ((ret = read_fpga_register(sdi, 1, ®1)) != SR_OK)
550 if (devc->fpga_variant == FPGA_VARIANT_ORIGINAL && (reg1 & ~0x20) != 0x08) {
551 sr_dbg("Invalid state at acquisition stop: 0x%02x != 0x08.", reg1 & ~0x20);
555 if ((ret = read_fpga_register(sdi, 8, ®8)) != SR_OK)
558 if ((ret = read_fpga_register(sdi, 9, ®9)) != SR_OK)
561 if (devc->fpga_variant == FPGA_VARIANT_ORIGINAL && reg1 & 0x20) {
562 sr_warn("FIFO overflow, capture data may be truncated.");
569 SR_PRIV int logic16_init_device(const struct sr_dev_inst *sdi)
572 struct dev_context *devc;
577 devc->cur_voltage_range = VOLTAGE_RANGE_UNKNOWN;
579 if ((ret = abort_acquisition_sync(sdi)) != SR_OK)
582 if ((ret = read_eeprom(sdi, 8, 8, devc->eeprom_data)) != SR_OK)
585 /* mcupro Saleae16 has firmware pre-stored in FPGA.
586 So, we can query it right away. */
587 if (read_fpga_register(sdi, 0, &version) == SR_OK &&
588 (version == 0x40 || version == 0x41)) {
589 sr_info("mcupro Saleae16 detected.");
590 devc->fpga_variant = FPGA_VARIANT_MCUPRO;
592 sr_info("Original Saleae Logic16 detected.");
593 devc->fpga_variant = FPGA_VARIANT_ORIGINAL;
596 ret = upload_fpga_bitstream(sdi, devc->selected_voltage_range);
603 static void finish_acquisition(struct sr_dev_inst *sdi)
605 struct sr_datafeed_packet packet;
606 struct dev_context *devc;
610 /* Terminate session. */
611 packet.type = SR_DF_END;
612 sr_session_send(devc->cb_data, &packet);
614 /* Remove fds from polling. */
615 usb_source_remove(sdi->session, devc->ctx);
617 devc->num_transfers = 0;
618 g_free(devc->transfers);
619 g_free(devc->convbuffer);
621 soft_trigger_logic_free(devc->stl);
626 static void free_transfer(struct libusb_transfer *transfer)
628 struct sr_dev_inst *sdi;
629 struct dev_context *devc;
632 sdi = transfer->user_data;
635 g_free(transfer->buffer);
636 transfer->buffer = NULL;
637 libusb_free_transfer(transfer);
639 for (i = 0; i < devc->num_transfers; i++) {
640 if (devc->transfers[i] == transfer) {
641 devc->transfers[i] = NULL;
646 devc->submitted_transfers--;
647 if (devc->submitted_transfers == 0)
648 finish_acquisition(sdi);
651 static void resubmit_transfer(struct libusb_transfer *transfer)
655 if ((ret = libusb_submit_transfer(transfer)) == LIBUSB_SUCCESS)
658 free_transfer(transfer);
659 /* TODO: Stop session? */
661 sr_err("%s: %s", __func__, libusb_error_name(ret));
664 static size_t convert_sample_data(struct dev_context *devc,
665 uint8_t *dest, size_t destcnt, const uint8_t *src, size_t srccnt)
667 uint16_t *channel_data;
670 uint16_t sample, channel_mask;
674 channel_data = devc->channel_data;
675 cur_channel = devc->cur_channel;
678 sample = src[0] | (src[1] << 8);
681 channel_mask = devc->channel_masks[cur_channel];
683 for (i = 15; i >= 0; --i, sample >>= 1)
685 channel_data[i] |= channel_mask;
687 if (++cur_channel == devc->num_channels) {
689 if (destcnt < 16 * 2) {
690 sr_err("Conversion buffer too small!");
693 memcpy(dest, channel_data, 16 * 2);
694 memset(channel_data, 0, 16 * 2);
701 devc->cur_channel = cur_channel;
706 SR_PRIV void logic16_receive_transfer(struct libusb_transfer *transfer)
708 gboolean packet_has_error = FALSE;
709 struct sr_datafeed_packet packet;
710 struct sr_datafeed_logic logic;
711 struct sr_dev_inst *sdi;
712 struct dev_context *devc;
713 size_t new_samples, num_samples;
715 int pre_trigger_samples;
717 sdi = transfer->user_data;
721 * If acquisition has already ended, just free any queued up
722 * transfer that come in.
724 if (devc->sent_samples < 0) {
725 free_transfer(transfer);
729 sr_info("receive_transfer(): status %s received %d bytes.",
730 libusb_error_name(transfer->status), transfer->actual_length);
732 switch (transfer->status) {
733 case LIBUSB_TRANSFER_NO_DEVICE:
734 devc->sent_samples = -2;
735 free_transfer(transfer);
737 case LIBUSB_TRANSFER_COMPLETED:
738 case LIBUSB_TRANSFER_TIMED_OUT: /* We may have received some data though. */
741 packet_has_error = TRUE;
745 if (transfer->actual_length & 1) {
746 sr_err("Got an odd number of bytes from the device. "
747 "This should not happen.");
748 /* Bail out right away. */
749 packet_has_error = TRUE;
750 devc->empty_transfer_count = MAX_EMPTY_TRANSFERS;
753 if (transfer->actual_length == 0 || packet_has_error) {
754 devc->empty_transfer_count++;
755 if (devc->empty_transfer_count > MAX_EMPTY_TRANSFERS) {
757 * The FX2 gave up. End the acquisition, the frontend
758 * will work out that the samplecount is short.
760 devc->sent_samples = -2;
761 free_transfer(transfer);
763 resubmit_transfer(transfer);
767 devc->empty_transfer_count = 0;
770 new_samples = convert_sample_data(devc, devc->convbuffer,
771 devc->convbuffer_size, transfer->buffer, transfer->actual_length);
773 if (new_samples > 0) {
774 if (devc->trigger_fired) {
775 /* Send the incoming transfer to the session bus. */
776 packet.type = SR_DF_LOGIC;
777 packet.payload = &logic;
778 if (devc->limit_samples &&
779 new_samples > devc->limit_samples - devc->sent_samples)
780 new_samples = devc->limit_samples - devc->sent_samples;
781 logic.length = new_samples * 2;
783 logic.data = devc->convbuffer;
784 sr_session_send(devc->cb_data, &packet);
785 devc->sent_samples += new_samples;
787 trigger_offset = soft_trigger_logic_check(devc->stl,
788 devc->convbuffer, new_samples * 2, &pre_trigger_samples);
789 if (trigger_offset > -1) {
790 devc->sent_samples += pre_trigger_samples;
791 packet.type = SR_DF_LOGIC;
792 packet.payload = &logic;
793 num_samples = new_samples - trigger_offset;
794 if (devc->limit_samples &&
795 num_samples > devc->limit_samples - devc->sent_samples)
796 num_samples = devc->limit_samples - devc->sent_samples;
797 logic.length = num_samples * 2;
799 logic.data = devc->convbuffer + trigger_offset * 2;
800 sr_session_send(devc->cb_data, &packet);
801 devc->sent_samples += num_samples;
803 devc->trigger_fired = TRUE;
807 if (devc->limit_samples &&
808 (uint64_t)devc->sent_samples >= devc->limit_samples) {
809 devc->sent_samples = -2;
810 free_transfer(transfer);
815 resubmit_transfer(transfer);