2 * This file is part of the libsigrok project.
4 * Copyright (C) 2013 Marcus Comstedt <marcus@mc.pp.se>
5 * Copyright (C) 2013 Bert Vermeulen <bert@biot.com>
6 * Copyright (C) 2012 Joel Holdsworth <joel@airwebreathe.org.uk>
8 * This program is free software: you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation, either version 3 of the License, or
11 * (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program. If not, see <http://www.gnu.org/licenses/>.
26 #include <glib/gstdio.h>
30 #include <libsigrok/libsigrok.h>
31 #include "libsigrok-internal.h"
34 #define FPGA_FIRMWARE_18 "saleae-logic16-fpga-18.bitstream"
35 #define FPGA_FIRMWARE_33 "saleae-logic16-fpga-33.bitstream"
37 #define MAX_SAMPLE_RATE SR_MHZ(100)
38 #define MAX_4CH_SAMPLE_RATE SR_MHZ(50)
39 #define MAX_7CH_SAMPLE_RATE SR_MHZ(40)
40 #define MAX_8CH_SAMPLE_RATE SR_MHZ(32)
41 #define MAX_10CH_SAMPLE_RATE SR_MHZ(25)
42 #define MAX_13CH_SAMPLE_RATE SR_MHZ(16)
44 #define BASE_CLOCK_0_FREQ SR_MHZ(100)
45 #define BASE_CLOCK_1_FREQ SR_MHZ(160)
47 #define COMMAND_START_ACQUISITION 1
48 #define COMMAND_ABORT_ACQUISITION_ASYNC 2
49 #define COMMAND_WRITE_EEPROM 6
50 #define COMMAND_READ_EEPROM 7
51 #define COMMAND_WRITE_LED_TABLE 0x7a
52 #define COMMAND_SET_LED_MODE 0x7b
53 #define COMMAND_RETURN_TO_BOOTLOADER 0x7c
54 #define COMMAND_ABORT_ACQUISITION_SYNC 0x7d
55 #define COMMAND_FPGA_UPLOAD_INIT 0x7e
56 #define COMMAND_FPGA_UPLOAD_SEND_DATA 0x7f
57 #define COMMAND_FPGA_WRITE_REGISTER 0x80
58 #define COMMAND_FPGA_READ_REGISTER 0x81
59 #define COMMAND_GET_REVID 0x82
61 #define WRITE_EEPROM_COOKIE1 0x42
62 #define WRITE_EEPROM_COOKIE2 0x55
63 #define READ_EEPROM_COOKIE1 0x33
64 #define READ_EEPROM_COOKIE2 0x81
65 #define ABORT_ACQUISITION_SYNC_PATTERN 0x55
67 #define MAX_EMPTY_TRANSFERS 64
69 /* Register mappings for old and new bitstream versions */
71 enum fpga_register_id {
72 FPGA_REGISTER_VERSION,
73 FPGA_REGISTER_STATUS_CONTROL,
74 FPGA_REGISTER_CHANNEL_SELECT_LOW,
75 FPGA_REGISTER_CHANNEL_SELECT_HIGH,
76 FPGA_REGISTER_SAMPLE_RATE_DIVISOR,
77 FPGA_REGISTER_LED_BRIGHTNESS,
78 FPGA_REGISTER_PRIMER_DATA1,
79 FPGA_REGISTER_PRIMER_CONTROL,
81 FPGA_REGISTER_PRIMER_DATA2,
82 FPGA_REGISTER_MAX = FPGA_REGISTER_PRIMER_DATA2
85 enum fpga_status_control_bit {
86 FPGA_STATUS_CONTROL_BIT_RUNNING,
87 FPGA_STATUS_CONTROL_BIT_UPDATE,
88 FPGA_STATUS_CONTROL_BIT_UNKNOWN1,
89 FPGA_STATUS_CONTROL_BIT_OVERFLOW,
90 FPGA_STATUS_CONTROL_BIT_UNKNOWN2,
91 FPGA_STATUS_CONTROL_BIT_MAX = FPGA_STATUS_CONTROL_BIT_UNKNOWN2
96 FPGA_MODE_BIT_UNKNOWN1,
97 FPGA_MODE_BIT_UNKNOWN2,
98 FPGA_MODE_BIT_MAX = FPGA_MODE_BIT_UNKNOWN2
101 static const uint8_t fpga_register_map_old[FPGA_REGISTER_MAX + 1] = {
102 [FPGA_REGISTER_VERSION] = 0,
103 [FPGA_REGISTER_STATUS_CONTROL] = 1,
104 [FPGA_REGISTER_CHANNEL_SELECT_LOW] = 2,
105 [FPGA_REGISTER_CHANNEL_SELECT_HIGH] = 3,
106 [FPGA_REGISTER_SAMPLE_RATE_DIVISOR] = 4,
107 [FPGA_REGISTER_LED_BRIGHTNESS] = 5,
108 [FPGA_REGISTER_PRIMER_DATA1] = 6,
109 [FPGA_REGISTER_PRIMER_CONTROL] = 7,
110 [FPGA_REGISTER_MODE] = 10,
111 [FPGA_REGISTER_PRIMER_DATA2] = 12,
114 static const uint8_t fpga_register_map_new[FPGA_REGISTER_MAX + 1] = {
115 [FPGA_REGISTER_VERSION] = 7,
116 [FPGA_REGISTER_STATUS_CONTROL] = 15,
117 [FPGA_REGISTER_CHANNEL_SELECT_LOW] = 1,
118 [FPGA_REGISTER_CHANNEL_SELECT_HIGH] = 6,
119 [FPGA_REGISTER_SAMPLE_RATE_DIVISOR] = 11,
120 [FPGA_REGISTER_LED_BRIGHTNESS] = 5,
121 [FPGA_REGISTER_PRIMER_DATA1] = 14,
122 [FPGA_REGISTER_PRIMER_CONTROL] = 2,
123 [FPGA_REGISTER_MODE] = 4,
124 [FPGA_REGISTER_PRIMER_DATA2] = 3,
127 static const uint8_t fpga_status_control_bit_map_old[FPGA_STATUS_CONTROL_BIT_MAX + 1] = {
128 [FPGA_STATUS_CONTROL_BIT_RUNNING] = 0x01,
129 [FPGA_STATUS_CONTROL_BIT_UPDATE] = 0x02,
130 [FPGA_STATUS_CONTROL_BIT_UNKNOWN1] = 0x08,
131 [FPGA_STATUS_CONTROL_BIT_OVERFLOW] = 0x20,
132 [FPGA_STATUS_CONTROL_BIT_UNKNOWN2] = 0x40,
135 static const uint8_t fpga_status_control_bit_map_new[FPGA_STATUS_CONTROL_BIT_MAX + 1] = {
136 [FPGA_STATUS_CONTROL_BIT_RUNNING] = 0x20,
137 [FPGA_STATUS_CONTROL_BIT_UPDATE] = 0x08,
138 [FPGA_STATUS_CONTROL_BIT_UNKNOWN1] = 0x10,
139 [FPGA_STATUS_CONTROL_BIT_OVERFLOW] = 0x01,
140 [FPGA_STATUS_CONTROL_BIT_UNKNOWN2] = 0x04,
143 static const uint8_t fpga_mode_bit_map_old[FPGA_MODE_BIT_MAX + 1] = {
144 [FPGA_MODE_BIT_CLOCK] = 0x01,
145 [FPGA_MODE_BIT_UNKNOWN1] = 0x40,
146 [FPGA_MODE_BIT_UNKNOWN2] = 0x80,
149 static const uint8_t fpga_mode_bit_map_new[FPGA_MODE_BIT_MAX + 1] = {
150 [FPGA_MODE_BIT_CLOCK] = 0x04,
151 [FPGA_MODE_BIT_UNKNOWN1] = 0x80,
152 [FPGA_MODE_BIT_UNKNOWN2] = 0x01,
155 #define FPGA_REG(x) \
156 (devc->fpga_register_map[FPGA_REGISTER_ ## x])
158 #define FPGA_STATUS_CONTROL(x) \
159 (devc->fpga_status_control_bit_map[FPGA_STATUS_CONTROL_BIT_ ## x])
161 #define FPGA_MODE(x) \
162 (devc->fpga_mode_bit_map[FPGA_MODE_BIT_ ## x])
164 static void encrypt(uint8_t *dest, const uint8_t *src, uint8_t cnt)
166 uint8_t state1 = 0x9b, state2 = 0x54;
170 for (i = 0; i < cnt; i++) {
172 t = (((v ^ state2 ^ 0x2b) - 0x05) ^ 0x35) - 0x39;
173 t = (((t ^ state1 ^ 0x5a) - 0xb0) ^ 0x38) - 0x45;
174 dest[i] = state2 = t;
179 static void decrypt(uint8_t *dest, const uint8_t *src, uint8_t cnt)
181 uint8_t state1 = 0x9b, state2 = 0x54;
185 for (i = 0; i < cnt; i++) {
187 t = (((v + 0x45) ^ 0x38) + 0xb0) ^ 0x5a ^ state1;
188 t = (((t + 0x39) ^ 0x35) + 0x05) ^ 0x2b ^ state2;
189 dest[i] = state1 = t;
194 static int do_ep1_command(const struct sr_dev_inst *sdi,
195 const uint8_t *command, uint8_t cmd_len,
196 uint8_t *reply, uint8_t reply_len)
199 struct sr_usb_dev_inst *usb;
204 if (cmd_len < 1 || cmd_len > 64 || reply_len > 64 ||
205 !command || (reply_len > 0 && !reply))
208 encrypt(buf, command, cmd_len);
210 ret = libusb_bulk_transfer(usb->devhdl, 1, buf, cmd_len, &xfer, 1000);
212 sr_dbg("Failed to send EP1 command 0x%02x: %s.",
213 command[0], libusb_error_name(ret));
216 if (xfer != cmd_len) {
217 sr_dbg("Failed to send EP1 command 0x%02x: incorrect length "
218 "%d != %d.", command[0], xfer, cmd_len);
225 ret = libusb_bulk_transfer(usb->devhdl, 0x80 | 1, buf, reply_len,
228 sr_dbg("Failed to receive reply to EP1 command 0x%02x: %s.",
229 command[0], libusb_error_name(ret));
232 if (xfer != reply_len) {
233 sr_dbg("Failed to receive reply to EP1 command 0x%02x: "
234 "incorrect length %d != %d.", command[0], xfer, reply_len);
238 decrypt(reply, buf, reply_len);
243 static int read_eeprom(const struct sr_dev_inst *sdi,
244 uint8_t address, uint8_t length, uint8_t *buf)
246 uint8_t command[5] = {
254 return do_ep1_command(sdi, command, 5, buf, length);
257 static int upload_led_table(const struct sr_dev_inst *sdi,
258 const uint8_t *table, uint8_t offset, uint8_t cnt)
260 uint8_t chunk, command[64];
263 if (cnt < 1 || cnt + offset > 64 || !table)
267 chunk = (cnt > 32 ? 32 : cnt);
269 command[0] = COMMAND_WRITE_LED_TABLE;
272 memcpy(command + 3, table, chunk);
274 ret = do_ep1_command(sdi, command, 3 + chunk, NULL, 0);
286 static int set_led_mode(const struct sr_dev_inst *sdi,
287 uint8_t animate, uint16_t t2reload, uint8_t div,
290 uint8_t command[6] = {
291 COMMAND_SET_LED_MODE,
299 return do_ep1_command(sdi, command, 6, NULL, 0);
302 static int read_fpga_register(const struct sr_dev_inst *sdi,
303 uint8_t address, uint8_t *value)
305 uint8_t command[3] = {
306 COMMAND_FPGA_READ_REGISTER,
311 return do_ep1_command(sdi, command, 3, value, 1);
314 static int write_fpga_registers(const struct sr_dev_inst *sdi,
315 uint8_t (*regs)[2], uint8_t cnt)
320 if (cnt < 1 || cnt > 31)
323 command[0] = COMMAND_FPGA_WRITE_REGISTER;
325 for (i = 0; i < cnt; i++) {
326 command[2 + 2 * i] = regs[i][0];
327 command[3 + 2 * i] = regs[i][1];
330 return do_ep1_command(sdi, command, 2 * (cnt + 1), NULL, 0);
333 static int write_fpga_register(const struct sr_dev_inst *sdi,
334 uint8_t address, uint8_t value)
336 uint8_t regs[2] = { address, value };
338 return write_fpga_registers(sdi, ®s, 1);
341 static uint8_t map_eeprom_data(uint8_t v)
343 return (((v ^ 0x80) + 0x44) ^ 0xd5) + 0x69;
346 static int setup_register_mapping(const struct sr_dev_inst *sdi)
348 struct dev_context *devc;
353 if (devc->fpga_variant != FPGA_VARIANT_MCUPRO) {
357 * Check for newer bitstream version by polling the
358 * version register at the old and new location.
361 if ((ret = read_fpga_register(sdi, 0 /* No mapping */, ®0)) != SR_OK)
364 if ((ret = read_fpga_register(sdi, 7 /* No mapping */, ®7)) != SR_OK)
367 if (reg0 == 0 && reg7 > 0x10) {
368 sr_info("Original Saleae Logic16 using new bitstream.");
369 devc->fpga_variant = FPGA_VARIANT_ORIGINAL_NEW_BITSTREAM;
371 sr_info("Original Saleae Logic16 using old bitstream.");
372 devc->fpga_variant = FPGA_VARIANT_ORIGINAL;
376 if (devc->fpga_variant == FPGA_VARIANT_ORIGINAL_NEW_BITSTREAM) {
377 devc->fpga_register_map = fpga_register_map_new;
378 devc->fpga_status_control_bit_map = fpga_status_control_bit_map_new;
379 devc->fpga_mode_bit_map = fpga_mode_bit_map_new;
381 devc->fpga_register_map = fpga_register_map_old;
382 devc->fpga_status_control_bit_map = fpga_status_control_bit_map_old;
383 devc->fpga_mode_bit_map = fpga_mode_bit_map_old;
389 static int prime_fpga(const struct sr_dev_inst *sdi)
391 struct dev_context *devc = sdi->priv;
392 uint8_t eeprom_data[16];
393 uint8_t old_mode_reg, version;
394 uint8_t regs[8][2] = {
395 {FPGA_REG(MODE), 0x00},
396 {FPGA_REG(MODE), FPGA_MODE(UNKNOWN1)},
397 {FPGA_REG(PRIMER_DATA2), 0},
398 {FPGA_REG(MODE), FPGA_MODE(UNKNOWN1) | FPGA_MODE(UNKNOWN2)},
399 {FPGA_REG(MODE), FPGA_MODE(UNKNOWN1)},
400 {FPGA_REG(PRIMER_DATA1), 0},
401 {FPGA_REG(PRIMER_CONTROL), 1},
402 {FPGA_REG(PRIMER_CONTROL), 0}
406 if ((ret = read_eeprom(sdi, 16, 16, eeprom_data)) != SR_OK)
409 if ((ret = read_fpga_register(sdi, FPGA_REG(MODE), &old_mode_reg)) != SR_OK)
412 regs[0][1] = (old_mode_reg &= ~FPGA_MODE(UNKNOWN2));
413 regs[1][1] |= old_mode_reg;
414 regs[3][1] |= old_mode_reg;
415 regs[4][1] |= old_mode_reg;
417 for (i = 0; i < 16; i++) {
418 regs[2][1] = eeprom_data[i];
419 regs[5][1] = map_eeprom_data(eeprom_data[i]);
421 ret = write_fpga_registers(sdi, ®s[2], 6);
423 ret = write_fpga_registers(sdi, ®s[0], 8);
428 if ((ret = write_fpga_register(sdi, FPGA_REG(MODE), old_mode_reg)) != SR_OK)
431 if ((ret = read_fpga_register(sdi, FPGA_REG(VERSION), &version)) != SR_OK)
434 if (version != 0x10 && version != 0x13 && version != 0x40 && version != 0x41) {
435 sr_err("Unsupported FPGA version: 0x%02x.", version);
442 static void make_heartbeat(uint8_t *table, int len)
446 memset(table, 0, len);
448 for (i = 0; i < 2; i++)
449 for (j = 0; j < len; j++)
450 *table++ = sin(j * G_PI / len) * 255;
453 static int configure_led(const struct sr_dev_inst *sdi)
458 make_heartbeat(table, 64);
459 if ((ret = upload_led_table(sdi, table, 0, 64)) != SR_OK)
462 return set_led_mode(sdi, 1, 6250, 0, 1);
465 static int upload_fpga_bitstream(const struct sr_dev_inst *sdi,
466 enum voltage_range vrange)
469 struct sr_resource bitstream;
470 struct dev_context *devc;
471 struct drv_context *drvc;
478 drvc = sdi->driver->context;
480 if (devc->cur_voltage_range == vrange)
483 if (devc->fpga_variant != FPGA_VARIANT_MCUPRO) {
485 case VOLTAGE_RANGE_18_33_V:
486 name = FPGA_FIRMWARE_18;
488 case VOLTAGE_RANGE_5_V:
489 name = FPGA_FIRMWARE_33;
492 sr_err("Unsupported voltage range.");
496 sr_info("Uploading FPGA bitstream '%s'.", name);
497 ret = sr_resource_open(drvc->sr_ctx, &bitstream,
498 SR_RESOURCE_FIRMWARE, name);
502 command[0] = COMMAND_FPGA_UPLOAD_INIT;
503 if ((ret = do_ep1_command(sdi, command, 1, NULL, 0)) != SR_OK) {
504 sr_resource_close(drvc->sr_ctx, &bitstream);
510 chunksize = sr_resource_read(drvc->sr_ctx, &bitstream,
511 &command[2], sizeof(command) - 2);
513 sr_resource_close(drvc->sr_ctx, &bitstream);
518 command[0] = COMMAND_FPGA_UPLOAD_SEND_DATA;
519 command[1] = chunksize;
521 ret = do_ep1_command(sdi, command, chunksize + 2,
524 sr_resource_close(drvc->sr_ctx, &bitstream);
529 sr_resource_close(drvc->sr_ctx, &bitstream);
530 sr_info("FPGA bitstream upload (%" PRIu64 " bytes) done.", sum);
533 /* This needs to be called before accessing any FPGA registers. */
534 if ((ret = setup_register_mapping(sdi)) != SR_OK)
537 if ((ret = prime_fpga(sdi)) != SR_OK)
540 if ((ret = configure_led(sdi)) != SR_OK)
543 devc->cur_voltage_range = vrange;
547 static int abort_acquisition_sync(const struct sr_dev_inst *sdi)
549 static const uint8_t command[2] = {
550 COMMAND_ABORT_ACQUISITION_SYNC,
551 ABORT_ACQUISITION_SYNC_PATTERN,
553 uint8_t reply, expected_reply;
556 if ((ret = do_ep1_command(sdi, command, 2, &reply, 1)) != SR_OK)
559 expected_reply = ~command[1];
560 if (reply != expected_reply) {
561 sr_err("Invalid response for abort acquisition command: "
562 "0x%02x != 0x%02x.", reply, expected_reply);
569 SR_PRIV int logic16_setup_acquisition(const struct sr_dev_inst *sdi,
570 uint64_t samplerate, uint16_t channels)
572 uint8_t clock_select, sta_con_reg, mode_reg;
574 int i, ret, nchan = 0;
575 struct dev_context *devc;
579 if (samplerate == 0 || samplerate > MAX_SAMPLE_RATE) {
580 sr_err("Unable to sample at %" PRIu64 "Hz.", samplerate);
584 if (BASE_CLOCK_0_FREQ % samplerate == 0 &&
585 (div = BASE_CLOCK_0_FREQ / samplerate) <= 256) {
587 } else if (BASE_CLOCK_1_FREQ % samplerate == 0 &&
588 (div = BASE_CLOCK_1_FREQ / samplerate) <= 256) {
591 sr_err("Unable to sample at %" PRIu64 "Hz.", samplerate);
595 for (i = 0; i < 16; i++)
596 if (channels & (1U << i))
599 if ((nchan >= 13 && samplerate > MAX_13CH_SAMPLE_RATE) ||
600 (nchan >= 10 && samplerate > MAX_10CH_SAMPLE_RATE) ||
601 (nchan >= 8 && samplerate > MAX_8CH_SAMPLE_RATE) ||
602 (nchan >= 7 && samplerate > MAX_7CH_SAMPLE_RATE) ||
603 (nchan >= 4 && samplerate > MAX_4CH_SAMPLE_RATE)) {
604 sr_err("Unable to sample at %" PRIu64 "Hz "
605 "with this many channels.", samplerate);
609 ret = upload_fpga_bitstream(sdi, devc->selected_voltage_range);
613 if ((ret = read_fpga_register(sdi, FPGA_REG(STATUS_CONTROL), &sta_con_reg)) != SR_OK)
616 /* Ignore FIFO overflow on previous capture */
617 sta_con_reg &= ~FPGA_STATUS_CONTROL(OVERFLOW);
619 if (devc->fpga_variant != FPGA_VARIANT_MCUPRO && sta_con_reg != FPGA_STATUS_CONTROL(UNKNOWN1)) {
620 sr_dbg("Invalid state at acquisition setup register 1: 0x%02x != 0x%02x. "
621 "Proceeding anyway.", sta_con_reg, FPGA_STATUS_CONTROL(UNKNOWN1));
624 if ((ret = write_fpga_register(sdi, FPGA_REG(STATUS_CONTROL), FPGA_STATUS_CONTROL(UNKNOWN2))) != SR_OK)
627 if ((ret = write_fpga_register(sdi, FPGA_REG(MODE), (clock_select? FPGA_MODE(CLOCK) : 0))) != SR_OK)
630 if ((ret = write_fpga_register(sdi, FPGA_REG(SAMPLE_RATE_DIVISOR), (uint8_t)(div - 1))) != SR_OK)
633 if ((ret = write_fpga_register(sdi, FPGA_REG(CHANNEL_SELECT_LOW), (uint8_t)(channels & 0xff))) != SR_OK)
636 if ((ret = write_fpga_register(sdi, FPGA_REG(CHANNEL_SELECT_HIGH), (uint8_t)(channels >> 8))) != SR_OK)
639 if ((ret = write_fpga_register(sdi, FPGA_REG(STATUS_CONTROL), FPGA_STATUS_CONTROL(UNKNOWN2) | FPGA_STATUS_CONTROL(UPDATE))) != SR_OK)
642 if ((ret = write_fpga_register(sdi, FPGA_REG(STATUS_CONTROL), FPGA_STATUS_CONTROL(UNKNOWN2))) != SR_OK)
645 if ((ret = read_fpga_register(sdi, FPGA_REG(STATUS_CONTROL), &sta_con_reg)) != SR_OK)
648 if (devc->fpga_variant != FPGA_VARIANT_MCUPRO && sta_con_reg != (FPGA_STATUS_CONTROL(UNKNOWN2) | FPGA_STATUS_CONTROL(UNKNOWN1))) {
649 sr_dbg("Invalid state at acquisition setup register 1: 0x%02x != 0x%02x. "
650 "Proceeding anyway.", sta_con_reg, FPGA_STATUS_CONTROL(UNKNOWN2) | FPGA_STATUS_CONTROL(UNKNOWN1));
653 if ((ret = read_fpga_register(sdi, FPGA_REG(MODE), &mode_reg)) != SR_OK)
656 if (devc->fpga_variant != FPGA_VARIANT_MCUPRO && mode_reg != (clock_select? FPGA_MODE(CLOCK) : 0)) {
657 sr_dbg("Invalid state at acquisition setup register 10: 0x%02x != 0x%02x. "
658 "Proceeding anyway.", mode_reg, (clock_select? FPGA_MODE(CLOCK) : 0));
664 SR_PRIV int logic16_start_acquisition(const struct sr_dev_inst *sdi)
666 static const uint8_t command[1] = {
667 COMMAND_START_ACQUISITION,
670 struct dev_context *devc;
674 if ((ret = do_ep1_command(sdi, command, 1, NULL, 0)) != SR_OK)
677 return write_fpga_register(sdi, FPGA_REG(STATUS_CONTROL), FPGA_STATUS_CONTROL(UNKNOWN2) | FPGA_STATUS_CONTROL(RUNNING));
680 SR_PRIV int logic16_abort_acquisition(const struct sr_dev_inst *sdi)
682 static const uint8_t command[1] = {
683 COMMAND_ABORT_ACQUISITION_ASYNC,
687 struct dev_context *devc;
691 if ((ret = do_ep1_command(sdi, command, 1, NULL, 0)) != SR_OK)
694 if ((ret = write_fpga_register(sdi, FPGA_REG(STATUS_CONTROL), 0x00)) != SR_OK)
697 if ((ret = read_fpga_register(sdi, FPGA_REG(STATUS_CONTROL), &sta_con_reg)) != SR_OK)
700 if (devc->fpga_variant != FPGA_VARIANT_MCUPRO && (sta_con_reg & ~FPGA_STATUS_CONTROL(OVERFLOW)) != FPGA_STATUS_CONTROL(UNKNOWN1)) {
701 sr_dbg("Invalid state at acquisition stop: 0x%02x != 0x%02x.", sta_con_reg & ~0x20, FPGA_STATUS_CONTROL(UNKNOWN1));
706 if (devc->fpga_variant == FPGA_VARIANT_ORIGINAL) {
709 if ((ret = read_fpga_register(sdi, 8, ®8)) != SR_OK)
712 if ((ret = read_fpga_register(sdi, 9, ®9)) != SR_OK)
716 if (devc->fpga_variant != FPGA_VARIANT_MCUPRO && sta_con_reg & FPGA_STATUS_CONTROL(OVERFLOW)) {
717 sr_warn("FIFO overflow, capture data may be truncated.");
724 SR_PRIV int logic16_init_device(const struct sr_dev_inst *sdi)
727 struct dev_context *devc;
732 devc->cur_voltage_range = VOLTAGE_RANGE_UNKNOWN;
734 if ((ret = abort_acquisition_sync(sdi)) != SR_OK)
737 if ((ret = read_eeprom(sdi, 8, 8, devc->eeprom_data)) != SR_OK)
740 /* mcupro Saleae16 has firmware pre-stored in FPGA.
741 So, we can query it right away. */
742 if (read_fpga_register(sdi, 0 /* No mapping */, &version) == SR_OK &&
743 (version == 0x40 || version == 0x41)) {
744 sr_info("mcupro Saleae16 detected.");
745 devc->fpga_variant = FPGA_VARIANT_MCUPRO;
747 sr_info("Original Saleae Logic16 detected.");
748 devc->fpga_variant = FPGA_VARIANT_ORIGINAL;
751 ret = upload_fpga_bitstream(sdi, devc->selected_voltage_range);
758 static void finish_acquisition(struct sr_dev_inst *sdi)
760 struct sr_datafeed_packet packet;
761 struct dev_context *devc;
765 /* Terminate session. */
766 packet.type = SR_DF_END;
767 sr_session_send(devc->cb_data, &packet);
769 /* Remove fds from polling. */
770 usb_source_remove(sdi->session, devc->ctx);
772 devc->num_transfers = 0;
773 g_free(devc->transfers);
774 g_free(devc->convbuffer);
776 soft_trigger_logic_free(devc->stl);
781 static void free_transfer(struct libusb_transfer *transfer)
783 struct sr_dev_inst *sdi;
784 struct dev_context *devc;
787 sdi = transfer->user_data;
790 g_free(transfer->buffer);
791 transfer->buffer = NULL;
792 libusb_free_transfer(transfer);
794 for (i = 0; i < devc->num_transfers; i++) {
795 if (devc->transfers[i] == transfer) {
796 devc->transfers[i] = NULL;
801 devc->submitted_transfers--;
802 if (devc->submitted_transfers == 0)
803 finish_acquisition(sdi);
806 static void resubmit_transfer(struct libusb_transfer *transfer)
810 if ((ret = libusb_submit_transfer(transfer)) == LIBUSB_SUCCESS)
813 free_transfer(transfer);
814 /* TODO: Stop session? */
816 sr_err("%s: %s", __func__, libusb_error_name(ret));
819 static size_t convert_sample_data(struct dev_context *devc,
820 uint8_t *dest, size_t destcnt, const uint8_t *src, size_t srccnt)
822 uint16_t *channel_data;
825 uint16_t sample, channel_mask;
829 channel_data = devc->channel_data;
830 cur_channel = devc->cur_channel;
833 sample = src[0] | (src[1] << 8);
836 channel_mask = devc->channel_masks[cur_channel];
838 for (i = 15; i >= 0; --i, sample >>= 1)
840 channel_data[i] |= channel_mask;
842 if (++cur_channel == devc->num_channels) {
844 if (destcnt < 16 * 2) {
845 sr_err("Conversion buffer too small!");
848 memcpy(dest, channel_data, 16 * 2);
849 memset(channel_data, 0, 16 * 2);
856 devc->cur_channel = cur_channel;
861 SR_PRIV void LIBUSB_CALL logic16_receive_transfer(struct libusb_transfer *transfer)
863 gboolean packet_has_error = FALSE;
864 struct sr_datafeed_packet packet;
865 struct sr_datafeed_logic logic;
866 struct sr_dev_inst *sdi;
867 struct dev_context *devc;
868 size_t new_samples, num_samples;
870 int pre_trigger_samples;
872 sdi = transfer->user_data;
876 * If acquisition has already ended, just free any queued up
877 * transfer that come in.
879 if (devc->sent_samples < 0) {
880 free_transfer(transfer);
884 sr_info("receive_transfer(): status %s received %d bytes.",
885 libusb_error_name(transfer->status), transfer->actual_length);
887 switch (transfer->status) {
888 case LIBUSB_TRANSFER_NO_DEVICE:
889 devc->sent_samples = -2;
890 free_transfer(transfer);
892 case LIBUSB_TRANSFER_COMPLETED:
893 case LIBUSB_TRANSFER_TIMED_OUT: /* We may have received some data though. */
896 packet_has_error = TRUE;
900 if (transfer->actual_length & 1) {
901 sr_err("Got an odd number of bytes from the device. "
902 "This should not happen.");
903 /* Bail out right away. */
904 packet_has_error = TRUE;
905 devc->empty_transfer_count = MAX_EMPTY_TRANSFERS;
908 if (transfer->actual_length == 0 || packet_has_error) {
909 devc->empty_transfer_count++;
910 if (devc->empty_transfer_count > MAX_EMPTY_TRANSFERS) {
912 * The FX2 gave up. End the acquisition, the frontend
913 * will work out that the samplecount is short.
915 devc->sent_samples = -2;
916 free_transfer(transfer);
918 resubmit_transfer(transfer);
922 devc->empty_transfer_count = 0;
925 new_samples = convert_sample_data(devc, devc->convbuffer,
926 devc->convbuffer_size, transfer->buffer, transfer->actual_length);
928 if (new_samples > 0) {
929 if (devc->trigger_fired) {
930 /* Send the incoming transfer to the session bus. */
931 packet.type = SR_DF_LOGIC;
932 packet.payload = &logic;
933 if (devc->limit_samples &&
934 new_samples > devc->limit_samples - devc->sent_samples)
935 new_samples = devc->limit_samples - devc->sent_samples;
936 logic.length = new_samples * 2;
938 logic.data = devc->convbuffer;
939 sr_session_send(devc->cb_data, &packet);
940 devc->sent_samples += new_samples;
942 trigger_offset = soft_trigger_logic_check(devc->stl,
943 devc->convbuffer, new_samples * 2, &pre_trigger_samples);
944 if (trigger_offset > -1) {
945 devc->sent_samples += pre_trigger_samples;
946 packet.type = SR_DF_LOGIC;
947 packet.payload = &logic;
948 num_samples = new_samples - trigger_offset;
949 if (devc->limit_samples &&
950 num_samples > devc->limit_samples - devc->sent_samples)
951 num_samples = devc->limit_samples - devc->sent_samples;
952 logic.length = num_samples * 2;
954 logic.data = devc->convbuffer + trigger_offset * 2;
955 sr_session_send(devc->cb_data, &packet);
956 devc->sent_samples += num_samples;
958 devc->trigger_fired = TRUE;
962 if (devc->limit_samples &&
963 (uint64_t)devc->sent_samples >= devc->limit_samples) {
964 devc->sent_samples = -2;
965 free_transfer(transfer);
970 resubmit_transfer(transfer);