2 * This file is part of the libsigrok project.
4 * Copyright (C) 2013 Marcus Comstedt <marcus@mc.pp.se>
5 * Copyright (C) 2013 Bert Vermeulen <bert@biot.com>
6 * Copyright (C) 2012 Joel Holdsworth <joel@airwebreathe.org.uk>
8 * This program is free software: you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation, either version 3 of the License, or
11 * (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program. If not, see <http://www.gnu.org/licenses/>.
25 #include <glib/gstdio.h>
29 #include <libsigrok/libsigrok.h>
30 #include "libsigrok-internal.h"
33 #define FPGA_FIRMWARE_18 FIRMWARE_DIR"/saleae-logic16-fpga-18.bitstream"
34 #define FPGA_FIRMWARE_33 FIRMWARE_DIR"/saleae-logic16-fpga-33.bitstream"
36 #define MAX_SAMPLE_RATE SR_MHZ(100)
37 #define MAX_4CH_SAMPLE_RATE SR_MHZ(50)
38 #define MAX_7CH_SAMPLE_RATE SR_MHZ(40)
39 #define MAX_8CH_SAMPLE_RATE SR_MHZ(32)
40 #define MAX_10CH_SAMPLE_RATE SR_MHZ(25)
41 #define MAX_13CH_SAMPLE_RATE SR_MHZ(16)
43 #define BASE_CLOCK_0_FREQ SR_MHZ(100)
44 #define BASE_CLOCK_1_FREQ SR_MHZ(160)
46 #define COMMAND_START_ACQUISITION 1
47 #define COMMAND_ABORT_ACQUISITION_ASYNC 2
48 #define COMMAND_WRITE_EEPROM 6
49 #define COMMAND_READ_EEPROM 7
50 #define COMMAND_WRITE_LED_TABLE 0x7a
51 #define COMMAND_SET_LED_MODE 0x7b
52 #define COMMAND_RETURN_TO_BOOTLOADER 0x7c
53 #define COMMAND_ABORT_ACQUISITION_SYNC 0x7d
54 #define COMMAND_FPGA_UPLOAD_INIT 0x7e
55 #define COMMAND_FPGA_UPLOAD_SEND_DATA 0x7f
56 #define COMMAND_FPGA_WRITE_REGISTER 0x80
57 #define COMMAND_FPGA_READ_REGISTER 0x81
58 #define COMMAND_GET_REVID 0x82
60 #define WRITE_EEPROM_COOKIE1 0x42
61 #define WRITE_EEPROM_COOKIE2 0x55
62 #define READ_EEPROM_COOKIE1 0x33
63 #define READ_EEPROM_COOKIE2 0x81
64 #define ABORT_ACQUISITION_SYNC_PATTERN 0x55
66 #define MAX_EMPTY_TRANSFERS 64
68 /* Register mappings for old and new bitstream versions */
70 enum fpga_register_id {
71 FPGA_REGISTER_VERSION,
72 FPGA_REGISTER_STATUS_CONTROL,
73 FPGA_REGISTER_CHANNEL_SELECT_LOW,
74 FPGA_REGISTER_CHANNEL_SELECT_HIGH,
75 FPGA_REGISTER_SAMPLE_RATE_DIVISOR,
76 FPGA_REGISTER_LED_BRIGHTNESS,
77 FPGA_REGISTER_PRIMER_DATA1,
78 FPGA_REGISTER_PRIMER_CONTROL,
80 FPGA_REGISTER_PRIMER_DATA2,
81 FPGA_REGISTER_MAX = FPGA_REGISTER_PRIMER_DATA2
84 enum fpga_status_control_bit {
85 FPGA_STATUS_CONTROL_BIT_RUNNING,
86 FPGA_STATUS_CONTROL_BIT_UPDATE,
87 FPGA_STATUS_CONTROL_BIT_UNKNOWN1,
88 FPGA_STATUS_CONTROL_BIT_OVERFLOW,
89 FPGA_STATUS_CONTROL_BIT_UNKNOWN2,
90 FPGA_STATUS_CONTROL_BIT_MAX = FPGA_STATUS_CONTROL_BIT_UNKNOWN2
95 FPGA_MODE_BIT_UNKNOWN1,
96 FPGA_MODE_BIT_UNKNOWN2,
97 FPGA_MODE_BIT_MAX = FPGA_MODE_BIT_UNKNOWN2
100 static const uint8_t fpga_register_map_old[FPGA_REGISTER_MAX + 1] = {
101 [FPGA_REGISTER_VERSION] = 0,
102 [FPGA_REGISTER_STATUS_CONTROL] = 1,
103 [FPGA_REGISTER_CHANNEL_SELECT_LOW] = 2,
104 [FPGA_REGISTER_CHANNEL_SELECT_HIGH] = 3,
105 [FPGA_REGISTER_SAMPLE_RATE_DIVISOR] = 4,
106 [FPGA_REGISTER_LED_BRIGHTNESS] = 5,
107 [FPGA_REGISTER_PRIMER_DATA1] = 6,
108 [FPGA_REGISTER_PRIMER_CONTROL] = 7,
109 [FPGA_REGISTER_MODE] = 10,
110 [FPGA_REGISTER_PRIMER_DATA2] = 12,
113 static const uint8_t fpga_register_map_new[FPGA_REGISTER_MAX + 1] = {
114 [FPGA_REGISTER_VERSION] = 7,
115 [FPGA_REGISTER_STATUS_CONTROL] = 15,
116 [FPGA_REGISTER_CHANNEL_SELECT_LOW] = 1,
117 [FPGA_REGISTER_CHANNEL_SELECT_HIGH] = 6,
118 [FPGA_REGISTER_SAMPLE_RATE_DIVISOR] = 11,
119 [FPGA_REGISTER_LED_BRIGHTNESS] = 5,
120 [FPGA_REGISTER_PRIMER_DATA1] = 14,
121 [FPGA_REGISTER_PRIMER_CONTROL] = 2,
122 [FPGA_REGISTER_MODE] = 4,
123 [FPGA_REGISTER_PRIMER_DATA2] = 3,
126 static const uint8_t fpga_status_control_bit_map_old[FPGA_STATUS_CONTROL_BIT_MAX + 1] = {
127 [FPGA_STATUS_CONTROL_BIT_RUNNING] = 0x01,
128 [FPGA_STATUS_CONTROL_BIT_UPDATE] = 0x02,
129 [FPGA_STATUS_CONTROL_BIT_UNKNOWN1] = 0x08,
130 [FPGA_STATUS_CONTROL_BIT_OVERFLOW] = 0x20,
131 [FPGA_STATUS_CONTROL_BIT_UNKNOWN2] = 0x40,
134 static const uint8_t fpga_status_control_bit_map_new[FPGA_STATUS_CONTROL_BIT_MAX + 1] = {
135 [FPGA_STATUS_CONTROL_BIT_RUNNING] = 0x20,
136 [FPGA_STATUS_CONTROL_BIT_UPDATE] = 0x08,
137 [FPGA_STATUS_CONTROL_BIT_UNKNOWN1] = 0x10,
138 [FPGA_STATUS_CONTROL_BIT_OVERFLOW] = 0x01,
139 [FPGA_STATUS_CONTROL_BIT_UNKNOWN2] = 0x04,
142 static const uint8_t fpga_mode_bit_map_old[FPGA_MODE_BIT_MAX + 1] = {
143 [FPGA_MODE_BIT_CLOCK] = 0x01,
144 [FPGA_MODE_BIT_UNKNOWN1] = 0x40,
145 [FPGA_MODE_BIT_UNKNOWN2] = 0x80,
148 static const uint8_t fpga_mode_bit_map_new[FPGA_MODE_BIT_MAX + 1] = {
149 [FPGA_MODE_BIT_CLOCK] = 0x04,
150 [FPGA_MODE_BIT_UNKNOWN1] = 0x80,
151 [FPGA_MODE_BIT_UNKNOWN2] = 0x01,
154 #define FPGA_REG(x) \
155 (devc->fpga_register_map[FPGA_REGISTER_ ## x])
157 #define FPGA_STATUS_CONTROL(x) \
158 (devc->fpga_status_control_bit_map[FPGA_STATUS_CONTROL_BIT_ ## x])
160 #define FPGA_MODE(x) \
161 (devc->fpga_mode_bit_map[FPGA_MODE_BIT_ ## x])
163 static void encrypt(uint8_t *dest, const uint8_t *src, uint8_t cnt)
165 uint8_t state1 = 0x9b, state2 = 0x54;
169 for (i = 0; i < cnt; i++) {
171 t = (((v ^ state2 ^ 0x2b) - 0x05) ^ 0x35) - 0x39;
172 t = (((t ^ state1 ^ 0x5a) - 0xb0) ^ 0x38) - 0x45;
173 dest[i] = state2 = t;
178 static void decrypt(uint8_t *dest, const uint8_t *src, uint8_t cnt)
180 uint8_t state1 = 0x9b, state2 = 0x54;
184 for (i = 0; i < cnt; i++) {
186 t = (((v + 0x45) ^ 0x38) + 0xb0) ^ 0x5a ^ state1;
187 t = (((t + 0x39) ^ 0x35) + 0x05) ^ 0x2b ^ state2;
188 dest[i] = state1 = t;
193 static int do_ep1_command(const struct sr_dev_inst *sdi,
194 const uint8_t *command, uint8_t cmd_len,
195 uint8_t *reply, uint8_t reply_len)
198 struct sr_usb_dev_inst *usb;
203 if (cmd_len < 1 || cmd_len > 64 || reply_len > 64 ||
204 !command || (reply_len > 0 && !reply))
207 encrypt(buf, command, cmd_len);
209 ret = libusb_bulk_transfer(usb->devhdl, 1, buf, cmd_len, &xfer, 1000);
211 sr_dbg("Failed to send EP1 command 0x%02x: %s.",
212 command[0], libusb_error_name(ret));
215 if (xfer != cmd_len) {
216 sr_dbg("Failed to send EP1 command 0x%02x: incorrect length "
217 "%d != %d.", xfer, cmd_len);
224 ret = libusb_bulk_transfer(usb->devhdl, 0x80 | 1, buf, reply_len,
227 sr_dbg("Failed to receive reply to EP1 command 0x%02x: %s.",
228 command[0], libusb_error_name(ret));
231 if (xfer != reply_len) {
232 sr_dbg("Failed to receive reply to EP1 command 0x%02x: "
233 "incorrect length %d != %d.", xfer, reply_len);
237 decrypt(reply, buf, reply_len);
242 static int read_eeprom(const struct sr_dev_inst *sdi,
243 uint8_t address, uint8_t length, uint8_t *buf)
245 uint8_t command[5] = {
253 return do_ep1_command(sdi, command, 5, buf, length);
256 static int upload_led_table(const struct sr_dev_inst *sdi,
257 const uint8_t *table, uint8_t offset, uint8_t cnt)
259 uint8_t chunk, command[64];
262 if (cnt < 1 || cnt + offset > 64 || !table)
266 chunk = (cnt > 32 ? 32 : cnt);
268 command[0] = COMMAND_WRITE_LED_TABLE;
271 memcpy(command + 3, table, chunk);
273 ret = do_ep1_command(sdi, command, 3 + chunk, NULL, 0);
285 static int set_led_mode(const struct sr_dev_inst *sdi,
286 uint8_t animate, uint16_t t2reload, uint8_t div,
289 uint8_t command[6] = {
290 COMMAND_SET_LED_MODE,
298 return do_ep1_command(sdi, command, 6, NULL, 0);
301 static int read_fpga_register(const struct sr_dev_inst *sdi,
302 uint8_t address, uint8_t *value)
304 uint8_t command[3] = {
305 COMMAND_FPGA_READ_REGISTER,
310 return do_ep1_command(sdi, command, 3, value, 1);
313 static int write_fpga_registers(const struct sr_dev_inst *sdi,
314 uint8_t (*regs)[2], uint8_t cnt)
319 if (cnt < 1 || cnt > 31)
322 command[0] = COMMAND_FPGA_WRITE_REGISTER;
324 for (i = 0; i < cnt; i++) {
325 command[2 + 2 * i] = regs[i][0];
326 command[3 + 2 * i] = regs[i][1];
329 return do_ep1_command(sdi, command, 2 * (cnt + 1), NULL, 0);
332 static int write_fpga_register(const struct sr_dev_inst *sdi,
333 uint8_t address, uint8_t value)
335 uint8_t regs[2] = { address, value };
337 return write_fpga_registers(sdi, ®s, 1);
340 static uint8_t map_eeprom_data(uint8_t v)
342 return (((v ^ 0x80) + 0x44) ^ 0xd5) + 0x69;
345 static int setup_register_mapping(const struct sr_dev_inst *sdi)
347 struct dev_context *devc;
352 if (devc->fpga_variant != FPGA_VARIANT_MCUPRO) {
356 * Check for newer bitstream version by polling the
357 * version register at the old and new location.
360 if ((ret = read_fpga_register(sdi, 0 /* No mapping */, ®0)) != SR_OK)
363 if ((ret = read_fpga_register(sdi, 7 /* No mapping */, ®7)) != SR_OK)
366 if (reg0 == 0 && reg7 > 0x10) {
367 sr_info("Original Saleae Logic16 using new bitstream.");
368 devc->fpga_variant = FPGA_VARIANT_ORIGINAL_NEW_BITSTREAM;
370 sr_info("Original Saleae Logic16 using old bitstream.");
371 devc->fpga_variant = FPGA_VARIANT_ORIGINAL;
375 if (devc->fpga_variant == FPGA_VARIANT_ORIGINAL_NEW_BITSTREAM) {
376 devc->fpga_register_map = fpga_register_map_new;
377 devc->fpga_status_control_bit_map = fpga_status_control_bit_map_new;
378 devc->fpga_mode_bit_map = fpga_mode_bit_map_new;
380 devc->fpga_register_map = fpga_register_map_old;
381 devc->fpga_status_control_bit_map = fpga_status_control_bit_map_old;
382 devc->fpga_mode_bit_map = fpga_mode_bit_map_old;
388 static int prime_fpga(const struct sr_dev_inst *sdi)
390 struct dev_context *devc = sdi->priv;
391 uint8_t eeprom_data[16];
392 uint8_t old_mode_reg, version;
393 uint8_t regs[8][2] = {
394 {FPGA_REG(MODE), 0x00},
395 {FPGA_REG(MODE), FPGA_MODE(UNKNOWN1)},
396 {FPGA_REG(PRIMER_DATA2), 0},
397 {FPGA_REG(MODE), FPGA_MODE(UNKNOWN1) | FPGA_MODE(UNKNOWN2)},
398 {FPGA_REG(MODE), FPGA_MODE(UNKNOWN1)},
399 {FPGA_REG(PRIMER_DATA1), 0},
400 {FPGA_REG(PRIMER_CONTROL), 1},
401 {FPGA_REG(PRIMER_CONTROL), 0}
405 if ((ret = read_eeprom(sdi, 16, 16, eeprom_data)) != SR_OK)
408 if ((ret = read_fpga_register(sdi, FPGA_REG(MODE), &old_mode_reg)) != SR_OK)
411 regs[0][1] = (old_mode_reg &= ~FPGA_MODE(UNKNOWN2));
412 regs[1][1] |= old_mode_reg;
413 regs[3][1] |= old_mode_reg;
414 regs[4][1] |= old_mode_reg;
416 for (i = 0; i < 16; i++) {
417 regs[2][1] = eeprom_data[i];
418 regs[5][1] = map_eeprom_data(eeprom_data[i]);
420 ret = write_fpga_registers(sdi, ®s[2], 6);
422 ret = write_fpga_registers(sdi, ®s[0], 8);
427 if ((ret = write_fpga_register(sdi, FPGA_REG(MODE), old_mode_reg)) != SR_OK)
430 if ((ret = read_fpga_register(sdi, FPGA_REG(VERSION), &version)) != SR_OK)
433 if (version != 0x10 && version != 0x13 && version != 0x40 && version != 0x41) {
434 sr_err("Unsupported FPGA version: 0x%02x.", version);
441 static void make_heartbeat(uint8_t *table, int len)
445 memset(table, 0, len);
447 for (i = 0; i < 2; i++)
448 for (j = 0; j < len; j++)
449 *table++ = sin(j * G_PI / len) * 255;
452 static int configure_led(const struct sr_dev_inst *sdi)
457 make_heartbeat(table, 64);
458 if ((ret = upload_led_table(sdi, table, 0, 64)) != SR_OK)
461 return set_led_mode(sdi, 1, 6250, 0, 1);
464 static int upload_fpga_bitstream(const struct sr_dev_inst *sdi,
465 enum voltage_range vrange)
467 struct dev_context *devc;
468 int offset, chunksize, ret;
469 const char *filename;
470 uint8_t len, buf[256 * 62], command[64];
475 if (devc->cur_voltage_range == vrange)
478 if (devc->fpga_variant != FPGA_VARIANT_MCUPRO) {
480 case VOLTAGE_RANGE_18_33_V:
481 filename = FPGA_FIRMWARE_18;
483 case VOLTAGE_RANGE_5_V:
484 filename = FPGA_FIRMWARE_33;
487 sr_err("Unsupported voltage range.");
491 sr_info("Uploading FPGA bitstream at %s.", filename);
492 if (!(fw = g_fopen(filename, "rb"))) {
493 sr_err("Unable to open bitstream file %s for reading: %s.",
494 filename, strerror(errno));
498 buf[0] = COMMAND_FPGA_UPLOAD_INIT;
499 if ((ret = do_ep1_command(sdi, buf, 1, NULL, 0)) != SR_OK) {
505 chunksize = fread(buf, 1, sizeof(buf), fw);
509 for (offset = 0; offset < chunksize; offset += 62) {
510 len = (offset + 62 > chunksize ?
511 chunksize - offset : 62);
512 command[0] = COMMAND_FPGA_UPLOAD_SEND_DATA;
514 memcpy(command + 2, buf + offset, len);
515 ret = do_ep1_command(sdi, command, len + 2, NULL, 0);
522 sr_info("Uploaded %d bytes.", chunksize);
525 sr_info("FPGA bitstream upload done.");
528 /* This needs to be called before accessing any FPGA registers. */
529 if ((ret = setup_register_mapping(sdi)) != SR_OK)
532 if ((ret = prime_fpga(sdi)) != SR_OK)
535 if ((ret = configure_led(sdi)) != SR_OK)
538 devc->cur_voltage_range = vrange;
542 static int abort_acquisition_sync(const struct sr_dev_inst *sdi)
544 static const uint8_t command[2] = {
545 COMMAND_ABORT_ACQUISITION_SYNC,
546 ABORT_ACQUISITION_SYNC_PATTERN,
548 uint8_t reply, expected_reply;
551 if ((ret = do_ep1_command(sdi, command, 2, &reply, 1)) != SR_OK)
554 expected_reply = ~command[1];
555 if (reply != expected_reply) {
556 sr_err("Invalid response for abort acquisition command: "
557 "0x%02x != 0x%02x.", reply, expected_reply);
564 SR_PRIV int logic16_setup_acquisition(const struct sr_dev_inst *sdi,
565 uint64_t samplerate, uint16_t channels)
567 uint8_t clock_select, sta_con_reg, mode_reg;
569 int i, ret, nchan = 0;
570 struct dev_context *devc;
574 if (samplerate == 0 || samplerate > MAX_SAMPLE_RATE) {
575 sr_err("Unable to sample at %" PRIu64 "Hz.", samplerate);
579 if (BASE_CLOCK_0_FREQ % samplerate == 0 &&
580 (div = BASE_CLOCK_0_FREQ / samplerate) <= 256) {
582 } else if (BASE_CLOCK_1_FREQ % samplerate == 0 &&
583 (div = BASE_CLOCK_1_FREQ / samplerate) <= 256) {
586 sr_err("Unable to sample at %" PRIu64 "Hz.", samplerate);
590 for (i = 0; i < 16; i++)
591 if (channels & (1U << i))
594 if ((nchan >= 13 && samplerate > MAX_13CH_SAMPLE_RATE) ||
595 (nchan >= 10 && samplerate > MAX_10CH_SAMPLE_RATE) ||
596 (nchan >= 8 && samplerate > MAX_8CH_SAMPLE_RATE) ||
597 (nchan >= 7 && samplerate > MAX_7CH_SAMPLE_RATE) ||
598 (nchan >= 4 && samplerate > MAX_4CH_SAMPLE_RATE)) {
599 sr_err("Unable to sample at %" PRIu64 "Hz "
600 "with this many channels.", samplerate);
604 ret = upload_fpga_bitstream(sdi, devc->selected_voltage_range);
608 if ((ret = read_fpga_register(sdi, FPGA_REG(STATUS_CONTROL), &sta_con_reg)) != SR_OK)
611 /* Ignore FIFO overflow on previous capture */
612 sta_con_reg &= ~FPGA_STATUS_CONTROL(OVERFLOW);
614 if (devc->fpga_variant != FPGA_VARIANT_MCUPRO && sta_con_reg != FPGA_STATUS_CONTROL(UNKNOWN1)) {
615 sr_dbg("Invalid state at acquisition setup register 1: 0x%02x != 0x%02x. "
616 "Proceeding anyway.", sta_con_reg, FPGA_STATUS_CONTROL(UNKNOWN1));
619 if ((ret = write_fpga_register(sdi, FPGA_REG(STATUS_CONTROL), FPGA_STATUS_CONTROL(UNKNOWN2))) != SR_OK)
622 if ((ret = write_fpga_register(sdi, FPGA_REG(MODE), (clock_select? FPGA_MODE(CLOCK) : 0))) != SR_OK)
625 if ((ret = write_fpga_register(sdi, FPGA_REG(SAMPLE_RATE_DIVISOR), (uint8_t)(div - 1))) != SR_OK)
628 if ((ret = write_fpga_register(sdi, FPGA_REG(CHANNEL_SELECT_LOW), (uint8_t)(channels & 0xff))) != SR_OK)
631 if ((ret = write_fpga_register(sdi, FPGA_REG(CHANNEL_SELECT_HIGH), (uint8_t)(channels >> 8))) != SR_OK)
634 if ((ret = write_fpga_register(sdi, FPGA_REG(STATUS_CONTROL), FPGA_STATUS_CONTROL(UNKNOWN2) | FPGA_STATUS_CONTROL(UPDATE))) != SR_OK)
637 if ((ret = write_fpga_register(sdi, FPGA_REG(STATUS_CONTROL), FPGA_STATUS_CONTROL(UNKNOWN2))) != SR_OK)
640 if ((ret = read_fpga_register(sdi, FPGA_REG(STATUS_CONTROL), &sta_con_reg)) != SR_OK)
643 if (devc->fpga_variant != FPGA_VARIANT_MCUPRO && sta_con_reg != (FPGA_STATUS_CONTROL(UNKNOWN2) | FPGA_STATUS_CONTROL(UNKNOWN1))) {
644 sr_dbg("Invalid state at acquisition setup register 1: 0x%02x != 0x%02x. "
645 "Proceeding anyway.", sta_con_reg, FPGA_STATUS_CONTROL(UNKNOWN2) | FPGA_STATUS_CONTROL(UNKNOWN1));
648 if ((ret = read_fpga_register(sdi, FPGA_REG(MODE), &mode_reg)) != SR_OK)
651 if (devc->fpga_variant != FPGA_VARIANT_MCUPRO && mode_reg != (clock_select? FPGA_MODE(CLOCK) : 0)) {
652 sr_dbg("Invalid state at acquisition setup register 10: 0x%02x != 0x%02x. "
653 "Proceeding anyway.", mode_reg, (clock_select? FPGA_MODE(CLOCK) : 0));
659 SR_PRIV int logic16_start_acquisition(const struct sr_dev_inst *sdi)
661 static const uint8_t command[1] = {
662 COMMAND_START_ACQUISITION,
665 struct dev_context *devc;
669 if ((ret = do_ep1_command(sdi, command, 1, NULL, 0)) != SR_OK)
672 return write_fpga_register(sdi, FPGA_REG(STATUS_CONTROL), FPGA_STATUS_CONTROL(UNKNOWN2) | FPGA_STATUS_CONTROL(RUNNING));
675 SR_PRIV int logic16_abort_acquisition(const struct sr_dev_inst *sdi)
677 static const uint8_t command[1] = {
678 COMMAND_ABORT_ACQUISITION_ASYNC,
682 struct dev_context *devc;
686 if ((ret = do_ep1_command(sdi, command, 1, NULL, 0)) != SR_OK)
689 if ((ret = write_fpga_register(sdi, FPGA_REG(STATUS_CONTROL), 0x00)) != SR_OK)
692 if ((ret = read_fpga_register(sdi, FPGA_REG(STATUS_CONTROL), &sta_con_reg)) != SR_OK)
695 if (devc->fpga_variant != FPGA_VARIANT_MCUPRO && (sta_con_reg & ~FPGA_STATUS_CONTROL(OVERFLOW)) != FPGA_STATUS_CONTROL(UNKNOWN1)) {
696 sr_dbg("Invalid state at acquisition stop: 0x%02x != 0x%02x.", sta_con_reg & ~0x20, FPGA_STATUS_CONTROL(UNKNOWN1));
701 if (devc->fpga_variant == FPGA_VARIANT_ORIGINAL) {
704 if ((ret = read_fpga_register(sdi, 8, ®8)) != SR_OK)
707 if ((ret = read_fpga_register(sdi, 9, ®9)) != SR_OK)
711 if (devc->fpga_variant != FPGA_VARIANT_MCUPRO && sta_con_reg & FPGA_STATUS_CONTROL(OVERFLOW)) {
712 sr_warn("FIFO overflow, capture data may be truncated.");
719 SR_PRIV int logic16_init_device(const struct sr_dev_inst *sdi)
722 struct dev_context *devc;
727 devc->cur_voltage_range = VOLTAGE_RANGE_UNKNOWN;
729 if ((ret = abort_acquisition_sync(sdi)) != SR_OK)
732 if ((ret = read_eeprom(sdi, 8, 8, devc->eeprom_data)) != SR_OK)
735 /* mcupro Saleae16 has firmware pre-stored in FPGA.
736 So, we can query it right away. */
737 if (read_fpga_register(sdi, 0 /* No mapping */, &version) == SR_OK &&
738 (version == 0x40 || version == 0x41)) {
739 sr_info("mcupro Saleae16 detected.");
740 devc->fpga_variant = FPGA_VARIANT_MCUPRO;
742 sr_info("Original Saleae Logic16 detected.");
743 devc->fpga_variant = FPGA_VARIANT_ORIGINAL;
746 ret = upload_fpga_bitstream(sdi, devc->selected_voltage_range);
753 static void finish_acquisition(struct sr_dev_inst *sdi)
755 struct sr_datafeed_packet packet;
756 struct dev_context *devc;
760 /* Terminate session. */
761 packet.type = SR_DF_END;
762 sr_session_send(devc->cb_data, &packet);
764 /* Remove fds from polling. */
765 usb_source_remove(sdi->session, devc->ctx);
767 devc->num_transfers = 0;
768 g_free(devc->transfers);
769 g_free(devc->convbuffer);
771 soft_trigger_logic_free(devc->stl);
776 static void free_transfer(struct libusb_transfer *transfer)
778 struct sr_dev_inst *sdi;
779 struct dev_context *devc;
782 sdi = transfer->user_data;
785 g_free(transfer->buffer);
786 transfer->buffer = NULL;
787 libusb_free_transfer(transfer);
789 for (i = 0; i < devc->num_transfers; i++) {
790 if (devc->transfers[i] == transfer) {
791 devc->transfers[i] = NULL;
796 devc->submitted_transfers--;
797 if (devc->submitted_transfers == 0)
798 finish_acquisition(sdi);
801 static void resubmit_transfer(struct libusb_transfer *transfer)
805 if ((ret = libusb_submit_transfer(transfer)) == LIBUSB_SUCCESS)
808 free_transfer(transfer);
809 /* TODO: Stop session? */
811 sr_err("%s: %s", __func__, libusb_error_name(ret));
814 static size_t convert_sample_data(struct dev_context *devc,
815 uint8_t *dest, size_t destcnt, const uint8_t *src, size_t srccnt)
817 uint16_t *channel_data;
820 uint16_t sample, channel_mask;
824 channel_data = devc->channel_data;
825 cur_channel = devc->cur_channel;
828 sample = src[0] | (src[1] << 8);
831 channel_mask = devc->channel_masks[cur_channel];
833 for (i = 15; i >= 0; --i, sample >>= 1)
835 channel_data[i] |= channel_mask;
837 if (++cur_channel == devc->num_channels) {
839 if (destcnt < 16 * 2) {
840 sr_err("Conversion buffer too small!");
843 memcpy(dest, channel_data, 16 * 2);
844 memset(channel_data, 0, 16 * 2);
851 devc->cur_channel = cur_channel;
856 SR_PRIV void LIBUSB_CALL logic16_receive_transfer(struct libusb_transfer *transfer)
858 gboolean packet_has_error = FALSE;
859 struct sr_datafeed_packet packet;
860 struct sr_datafeed_logic logic;
861 struct sr_dev_inst *sdi;
862 struct dev_context *devc;
863 size_t new_samples, num_samples;
865 int pre_trigger_samples;
867 sdi = transfer->user_data;
871 * If acquisition has already ended, just free any queued up
872 * transfer that come in.
874 if (devc->sent_samples < 0) {
875 free_transfer(transfer);
879 sr_info("receive_transfer(): status %s received %d bytes.",
880 libusb_error_name(transfer->status), transfer->actual_length);
882 switch (transfer->status) {
883 case LIBUSB_TRANSFER_NO_DEVICE:
884 devc->sent_samples = -2;
885 free_transfer(transfer);
887 case LIBUSB_TRANSFER_COMPLETED:
888 case LIBUSB_TRANSFER_TIMED_OUT: /* We may have received some data though. */
891 packet_has_error = TRUE;
895 if (transfer->actual_length & 1) {
896 sr_err("Got an odd number of bytes from the device. "
897 "This should not happen.");
898 /* Bail out right away. */
899 packet_has_error = TRUE;
900 devc->empty_transfer_count = MAX_EMPTY_TRANSFERS;
903 if (transfer->actual_length == 0 || packet_has_error) {
904 devc->empty_transfer_count++;
905 if (devc->empty_transfer_count > MAX_EMPTY_TRANSFERS) {
907 * The FX2 gave up. End the acquisition, the frontend
908 * will work out that the samplecount is short.
910 devc->sent_samples = -2;
911 free_transfer(transfer);
913 resubmit_transfer(transfer);
917 devc->empty_transfer_count = 0;
920 new_samples = convert_sample_data(devc, devc->convbuffer,
921 devc->convbuffer_size, transfer->buffer, transfer->actual_length);
923 if (new_samples > 0) {
924 if (devc->trigger_fired) {
925 /* Send the incoming transfer to the session bus. */
926 packet.type = SR_DF_LOGIC;
927 packet.payload = &logic;
928 if (devc->limit_samples &&
929 new_samples > devc->limit_samples - devc->sent_samples)
930 new_samples = devc->limit_samples - devc->sent_samples;
931 logic.length = new_samples * 2;
933 logic.data = devc->convbuffer;
934 sr_session_send(devc->cb_data, &packet);
935 devc->sent_samples += new_samples;
937 trigger_offset = soft_trigger_logic_check(devc->stl,
938 devc->convbuffer, new_samples * 2, &pre_trigger_samples);
939 if (trigger_offset > -1) {
940 devc->sent_samples += pre_trigger_samples;
941 packet.type = SR_DF_LOGIC;
942 packet.payload = &logic;
943 num_samples = new_samples - trigger_offset;
944 if (devc->limit_samples &&
945 num_samples > devc->limit_samples - devc->sent_samples)
946 num_samples = devc->limit_samples - devc->sent_samples;
947 logic.length = num_samples * 2;
949 logic.data = devc->convbuffer + trigger_offset * 2;
950 sr_session_send(devc->cb_data, &packet);
951 devc->sent_samples += num_samples;
953 devc->trigger_fired = TRUE;
957 if (devc->limit_samples &&
958 (uint64_t)devc->sent_samples >= devc->limit_samples) {
959 devc->sent_samples = -2;
960 free_transfer(transfer);
965 resubmit_transfer(transfer);