2 * This file is part of the libsigrok project.
4 * Copyright (C) 2013 Bert Vermeulen <bert@biot.com>
6 * This program is free software: you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation, either version 3 of the License, or
9 * (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program. If not, see <http://www.gnu.org/licenses/>.
23 static const uint32_t devopts[] = {
24 SR_CONF_LOGIC_ANALYZER,
25 SR_CONF_LIMIT_SAMPLES | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST,
26 SR_CONF_SAMPLERATE | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST,
27 SR_CONF_TRIGGER_MATCH | SR_CONF_LIST,
28 SR_CONF_CAPTURE_RATIO | SR_CONF_GET | SR_CONF_SET,
29 SR_CONF_PATTERN_MODE | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST,
30 SR_CONF_EXTERNAL_CLOCK | SR_CONF_GET | SR_CONF_SET,
31 SR_CONF_SWAP | SR_CONF_SET,
32 SR_CONF_RLE | SR_CONF_GET | SR_CONF_SET,
35 static const int32_t trigger_matches[] = {
42 #define STR_PATTERN_NONE "None"
43 #define STR_PATTERN_EXTERNAL "External"
44 #define STR_PATTERN_INTERNAL "Internal"
46 /* Supported methods of test pattern outputs */
49 * Capture pins 31:16 (unbuffered wing) output a test pattern
50 * that can captured on pins 0:15.
54 /** Route test pattern internally to capture buffer. */
58 static const char *patterns[] = {
64 /* Channels are numbered 0-31 (on the PCB silkscreen). */
65 SR_PRIV const char *p_ols_channel_names[] = {
66 "0", "1", "2", "3", "4", "5", "6", "7", "8", "9", "10", "11", "12",
67 "13", "14", "15", "16", "17", "18", "19", "20", "21", "22", "23",
68 "24", "25", "26", "27", "28", "29", "30", "31",
71 /* Default supported samplerates, can be overridden by device metadata. */
72 static const uint64_t samplerates[] = {
78 SR_PRIV struct sr_dev_driver p_ols_driver_info;
80 static int init(struct sr_dev_driver *di, struct sr_context *sr_ctx)
82 return std_init(sr_ctx, di, LOG_PREFIX);
85 static GSList *scan(struct sr_dev_driver *di, GSList *options)
87 struct sr_dev_inst *sdi;
88 struct drv_context *drvc;
89 struct dev_context *devc;
101 /* Allocate memory for our private device context. */
102 devc = g_malloc0(sizeof(struct dev_context));
104 /* Device-specific settings */
105 devc->max_samplebytes = devc->max_samplerate = devc->protocol_version = 0;
107 /* Acquisition settings */
108 devc->limit_samples = devc->capture_ratio = 0;
109 devc->trigger_at = -1;
110 devc->channel_mask = 0xffffffff;
113 /* Allocate memory for the incoming ftdi data. */
114 devc->ftdi_buf = g_malloc0(FTDI_BUF_SIZE);
116 /* Allocate memory for the FTDI context (ftdic) and initialize it. */
117 if (!(devc->ftdic = ftdi_new())) {
118 sr_err("Failed to initialize libftdi.");
119 goto err_free_ftdi_buf;;
122 /* Try to open the FTDI device */
123 if (p_ols_open(devc) != SR_OK) {
127 /* The discovery procedure is like this: first send the Reset
128 * command (0x00) 5 times, since the device could be anywhere
129 * in a 5-byte command. Then send the ID command (0x02).
130 * If the device responds with 4 bytes ("OLS1" or "SLA1"), we
135 for (i = 0; i < 5; i++) {
136 if ((ret = write_shortcommand(devc, CMD_RESET)) != SR_OK) {
141 sr_err("Could not reset device. Quitting.");
142 goto err_close_ftdic;
144 write_shortcommand(devc, CMD_ID);
146 /* Read the response data. */
147 bytes_read = ftdi_read_data(devc->ftdic, (uint8_t *)buf, 4);
148 if (bytes_read < 0) {
149 sr_err("Failed to read FTDI data (%d): %s.",
150 bytes_read, ftdi_get_error_string(devc->ftdic));
151 goto err_close_ftdic;
153 if (bytes_read == 0) {
154 goto err_close_ftdic;
157 if (strncmp(buf, "1SLO", 4) && strncmp(buf, "1ALS", 4))
158 goto err_close_ftdic;
160 /* Definitely using the OLS protocol, check if it supports
161 * the metadata command.
163 write_shortcommand(devc, CMD_METADATA);
165 /* Read the metadata. */
166 bytes_read = ftdi_read_data(devc->ftdic, (uint8_t *)buf, 64);
167 if (bytes_read < 0) {
168 sr_err("Failed to read FTDI data (%d): %s.",
169 bytes_read, ftdi_get_error_string(devc->ftdic));
170 goto err_close_ftdic;
172 if (bytes_read == 0) {
173 goto err_close_ftdic;
176 /* Close device. We'll reopen it again when we need it. */
179 /* Parse the metadata. */
180 sdi = p_ols_get_metadata((uint8_t *)buf, bytes_read, devc);
182 /* Configure samplerate and divider. */
183 if (p_ols_set_samplerate(sdi, DEFAULT_SAMPLERATE) != SR_OK)
184 sr_dbg("Failed to set default samplerate (%"PRIu64").",
187 drvc->instances = g_slist_append(drvc->instances, sdi);
188 devices = g_slist_append(devices, sdi);
195 ftdi_free(devc->ftdic); /* NOT free() or g_free()! */
197 g_free(devc->ftdi_buf);
203 static GSList *dev_list(const struct sr_dev_driver *di)
205 return ((struct drv_context *)(di->context))->instances;
208 static void clear_helper(void *priv)
210 struct dev_context *devc;
214 ftdi_free(devc->ftdic);
215 g_free(devc->ftdi_buf);
218 static int dev_clear(const struct sr_dev_driver *di)
220 return std_dev_clear(di, clear_helper);
223 static int config_get(uint32_t key, GVariant **data, const struct sr_dev_inst *sdi,
224 const struct sr_channel_group *cg)
226 struct dev_context *devc;
235 case SR_CONF_SAMPLERATE:
236 *data = g_variant_new_uint64(devc->cur_samplerate);
238 case SR_CONF_CAPTURE_RATIO:
239 *data = g_variant_new_uint64(devc->capture_ratio);
241 case SR_CONF_LIMIT_SAMPLES:
242 *data = g_variant_new_uint64(devc->limit_samples);
244 case SR_CONF_PATTERN_MODE:
245 if (devc->flag_reg & FLAG_EXTERNAL_TEST_MODE)
246 *data = g_variant_new_string(STR_PATTERN_EXTERNAL);
247 else if (devc->flag_reg & FLAG_INTERNAL_TEST_MODE)
248 *data = g_variant_new_string(STR_PATTERN_INTERNAL);
250 *data = g_variant_new_string(STR_PATTERN_NONE);
253 *data = g_variant_new_boolean(devc->flag_reg & FLAG_RLE ? TRUE : FALSE);
255 case SR_CONF_EXTERNAL_CLOCK:
256 *data = g_variant_new_boolean(devc->flag_reg & FLAG_CLOCK_EXTERNAL ? TRUE : FALSE);
265 static int config_set(uint32_t key, GVariant *data, const struct sr_dev_inst *sdi,
266 const struct sr_channel_group *cg)
268 struct dev_context *devc;
276 if (sdi->status != SR_ST_ACTIVE)
277 return SR_ERR_DEV_CLOSED;
282 case SR_CONF_SAMPLERATE:
283 tmp_u64 = g_variant_get_uint64(data);
284 if (tmp_u64 < samplerates[0] || tmp_u64 > samplerates[1])
285 return SR_ERR_SAMPLERATE;
286 ret = p_ols_set_samplerate(sdi, g_variant_get_uint64(data));
288 case SR_CONF_LIMIT_SAMPLES:
289 tmp_u64 = g_variant_get_uint64(data);
290 if (tmp_u64 < MIN_NUM_SAMPLES)
292 devc->limit_samples = tmp_u64;
295 case SR_CONF_CAPTURE_RATIO:
296 devc->capture_ratio = g_variant_get_uint64(data);
297 if (devc->capture_ratio < 0 || devc->capture_ratio > 100)
302 case SR_CONF_EXTERNAL_CLOCK:
303 if (g_variant_get_boolean(data)) {
304 sr_info("Enabling external clock.");
305 devc->flag_reg |= FLAG_CLOCK_EXTERNAL;
307 sr_info("Disabled external clock.");
308 devc->flag_reg &= ~FLAG_CLOCK_EXTERNAL;
312 case SR_CONF_PATTERN_MODE:
313 stropt = g_variant_get_string(data, NULL);
316 if (!strcmp(stropt, STR_PATTERN_NONE)) {
317 sr_info("Disabling test modes.");
319 }else if (!strcmp(stropt, STR_PATTERN_INTERNAL)) {
320 sr_info("Enabling internal test mode.");
321 flag = FLAG_INTERNAL_TEST_MODE;
322 } else if (!strcmp(stropt, STR_PATTERN_EXTERNAL)) {
323 sr_info("Enabling external test mode.");
324 flag = FLAG_EXTERNAL_TEST_MODE;
328 if (flag != 0xffff) {
329 devc->flag_reg &= ~(FLAG_INTERNAL_TEST_MODE | FLAG_EXTERNAL_TEST_MODE);
330 devc->flag_reg |= flag;
334 if (g_variant_get_boolean(data)) {
335 sr_info("Enabling channel swapping.");
336 devc->flag_reg |= FLAG_SWAP_CHANNELS;
338 sr_info("Disabling channel swapping.");
339 devc->flag_reg &= ~FLAG_SWAP_CHANNELS;
345 if (g_variant_get_boolean(data)) {
346 sr_info("Enabling RLE.");
347 devc->flag_reg |= FLAG_RLE;
349 sr_info("Disabling RLE.");
350 devc->flag_reg &= ~FLAG_RLE;
361 static int config_list(uint32_t key, GVariant **data, const struct sr_dev_inst *sdi,
362 const struct sr_channel_group *cg)
364 struct dev_context *devc;
365 GVariant *gvar, *grange[2];
367 int num_pols_changrp, i;
372 case SR_CONF_DEVICE_OPTIONS:
373 *data = g_variant_new_fixed_array(G_VARIANT_TYPE_UINT32,
374 devopts, ARRAY_SIZE(devopts), sizeof(uint32_t));
376 case SR_CONF_SAMPLERATE:
377 g_variant_builder_init(&gvb, G_VARIANT_TYPE("a{sv}"));
378 gvar = g_variant_new_fixed_array(G_VARIANT_TYPE("t"), samplerates,
379 ARRAY_SIZE(samplerates), sizeof(uint64_t));
380 g_variant_builder_add(&gvb, "{sv}", "samplerate-steps", gvar);
381 *data = g_variant_builder_end(&gvb);
383 case SR_CONF_TRIGGER_MATCH:
384 *data = g_variant_new_fixed_array(G_VARIANT_TYPE_INT32,
385 trigger_matches, ARRAY_SIZE(trigger_matches),
388 case SR_CONF_PATTERN_MODE:
389 *data = g_variant_new_strv(patterns, ARRAY_SIZE(patterns));
391 case SR_CONF_LIMIT_SAMPLES:
395 if (devc->flag_reg & FLAG_RLE)
397 if (devc->max_samplebytes == 0)
398 /* Device didn't specify sample memory size in metadata. */
401 * Channel groups are turned off if no channels in that group are
402 * enabled, making more room for samples for the enabled group.
404 pols_channel_mask(sdi);
405 num_pols_changrp = 0;
406 for (i = 0; i < 4; i++) {
407 if (devc->channel_mask & (0xff << (i * 8)))
410 /* 3 channel groups takes as many bytes as 4 channel groups */
411 if (num_pols_changrp == 3)
412 num_pols_changrp = 4;
413 grange[0] = g_variant_new_uint64(MIN_NUM_SAMPLES);
414 if (num_pols_changrp)
415 grange[1] = g_variant_new_uint64(devc->max_samplebytes / num_pols_changrp);
417 grange[1] = g_variant_new_uint64(MIN_NUM_SAMPLES);
418 *data = g_variant_new_tuple(grange, 2);
427 static int dev_open(struct sr_dev_inst *sdi)
429 struct dev_context *devc;
433 if (p_ols_open(devc) != SR_OK) {
436 sdi->status = SR_ST_ACTIVE;
441 static int dev_close(struct sr_dev_inst *sdi)
444 struct dev_context *devc;
449 if (sdi->status == SR_ST_ACTIVE) {
450 sr_dbg("Status ACTIVE, closing device.");
451 ret = p_ols_close(devc);
453 sr_spew("Status not ACTIVE, nothing to do.");
456 sdi->status = SR_ST_INACTIVE;
461 static int set_trigger(const struct sr_dev_inst *sdi, int stage)
463 struct dev_context *devc;
468 cmd = CMD_SET_TRIGGER_MASK + stage * 4;
469 arg[0] = devc->trigger_mask[stage] & 0xff;
470 arg[1] = (devc->trigger_mask[stage] >> 8) & 0xff;
471 arg[2] = (devc->trigger_mask[stage] >> 16) & 0xff;
472 arg[3] = (devc->trigger_mask[stage] >> 24) & 0xff;
473 if (write_longcommand(devc, cmd, arg) != SR_OK)
476 cmd = CMD_SET_TRIGGER_VALUE + stage * 4;
477 arg[0] = devc->trigger_value[stage] & 0xff;
478 arg[1] = (devc->trigger_value[stage] >> 8) & 0xff;
479 arg[2] = (devc->trigger_value[stage] >> 16) & 0xff;
480 arg[3] = (devc->trigger_value[stage] >> 24) & 0xff;
481 if (write_longcommand(devc, cmd, arg) != SR_OK)
484 cmd = CMD_SET_TRIGGER_CONFIG + stage * 4;
485 arg[0] = arg[1] = arg[3] = 0x00;
487 if (stage == devc->num_stages)
488 /* Last stage, fire when this one matches. */
489 arg[3] |= TRIGGER_START;
490 if (write_longcommand(devc, cmd, arg) != SR_OK)
493 cmd = CMD_SET_TRIGGER_EDGE + stage * 4;
494 arg[0] = devc->trigger_edge[stage] & 0xff;
495 arg[1] = (devc->trigger_edge[stage] >> 8) & 0xff;
496 arg[2] = (devc->trigger_edge[stage] >> 16) & 0xff;
497 arg[3] = (devc->trigger_edge[stage] >> 24) & 0xff;
498 if (write_longcommand(devc, cmd, arg) != SR_OK)
504 static int disable_trigger(const struct sr_dev_inst *sdi, int stage)
506 struct dev_context *devc;
511 cmd = CMD_SET_TRIGGER_MASK + stage * 4;
512 arg[0] = arg[1] = arg[2] = arg[3] = 0x00;
513 if (write_longcommand(devc, cmd, arg) != SR_OK)
516 cmd = CMD_SET_TRIGGER_VALUE + stage * 4;
517 if (write_longcommand(devc, cmd, arg) != SR_OK)
520 cmd = CMD_SET_TRIGGER_CONFIG + stage * 4;
522 if (write_longcommand(devc, cmd, arg) != SR_OK)
525 cmd = CMD_SET_TRIGGER_EDGE + stage * 4;
527 if (write_longcommand(devc, cmd, arg) != SR_OK)
533 static int dev_acquisition_start(const struct sr_dev_inst *sdi)
535 struct dev_context *devc;
536 uint32_t samplecount, readcount, delaycount;
537 uint8_t pols_changrp_mask, arg[4];
539 int num_pols_changrp, samplespercount;
542 if (sdi->status != SR_ST_ACTIVE)
543 return SR_ERR_DEV_CLOSED;
547 pols_channel_mask(sdi);
550 * Enable/disable channel groups in the flag register according to the
551 * channel mask. Calculate this here, because num_pols_changrp is
552 * needed to limit readcount.
554 pols_changrp_mask = 0;
555 num_pols_changrp = 0;
556 for (i = 0; i < 4; i++) {
557 if (devc->channel_mask & (0xff << (i * 8))) {
558 pols_changrp_mask |= (1 << i);
562 /* 3 channel groups takes as many bytes as 4 channel groups */
563 if (num_pols_changrp == 3)
564 num_pols_changrp = 4;
565 /* maximum number of samples (or RLE counts) the buffer memory can hold */
566 devc->max_samples = devc->max_samplebytes / num_pols_changrp;
569 * Limit readcount to prevent reading past the end of the hardware
572 sr_dbg("max_samples = %d", devc->max_samples);
573 sr_dbg("limit_samples = %" PRIu64, devc->limit_samples);
574 samplecount = MIN(devc->max_samples, devc->limit_samples);
575 sr_dbg("Samplecount = %d", samplecount);
577 /* In demux mode the OLS is processing two samples per clock */
578 if (devc->flag_reg & FLAG_DEMUX) {
585 readcount = samplecount / samplespercount;
587 /* Rather read too many samples than too few. */
588 if (samplecount % samplespercount != 0)
591 /* Basic triggers. */
592 if (pols_convert_trigger(sdi) != SR_OK) {
593 sr_err("Failed to configure channels.");
597 if (devc->num_stages > 0) {
598 delaycount = readcount * (1 - devc->capture_ratio / 100.0);
599 devc->trigger_at = (readcount - delaycount) * samplespercount - devc->num_stages;
600 for (i = 0; i < NUM_TRIGGER_STAGES; i++) {
601 if (i <= devc->num_stages) {
602 sr_dbg("Setting p-ols stage %d trigger.", i);
603 if ((ret = set_trigger(sdi, i)) != SR_OK)
607 sr_dbg("Disabling p-ols stage %d trigger.", i);
608 if ((ret = disable_trigger(sdi, i)) != SR_OK)
613 /* No triggers configured, force trigger on first stage. */
614 sr_dbg("Forcing trigger at stage 0.");
615 if ((ret = set_trigger(sdi, 0)) != SR_OK)
617 delaycount = readcount;
621 sr_dbg("Setting samplerate to %" PRIu64 "Hz (divider %u)",
622 devc->cur_samplerate, devc->cur_samplerate_divider);
623 arg[0] = devc->cur_samplerate_divider & 0xff;
624 arg[1] = (devc->cur_samplerate_divider & 0xff00) >> 8;
625 arg[2] = (devc->cur_samplerate_divider & 0xff0000) >> 16;
627 if (write_longcommand(devc, CMD_SET_DIVIDER, arg) != SR_OK)
630 /* Send extended sample limit and pre/post-trigger capture ratio. */
631 arg[0] = ((readcount - 1) & 0xff);
632 arg[1] = ((readcount - 1) & 0xff00) >> 8;
633 arg[2] = ((readcount - 1) & 0xff0000) >> 16;
634 arg[3] = ((readcount - 1) & 0xff000000) >> 24;
635 if (write_longcommand(devc, CMD_CAPTURE_DELAY, arg) != SR_OK)
637 arg[0] = ((delaycount - 1) & 0xff);
638 arg[1] = ((delaycount - 1) & 0xff00) >> 8;
639 arg[2] = ((delaycount - 1) & 0xff0000) >> 16;
640 arg[3] = ((delaycount - 1) & 0xff000000) >> 24;
641 if (write_longcommand(devc, CMD_CAPTURE_COUNT, arg) != SR_OK)
645 sr_dbg("Setting intpat %s, extpat %s, RLE %s, noise_filter %s, demux %s",
646 devc->flag_reg & FLAG_INTERNAL_TEST_MODE ? "on": "off",
647 devc->flag_reg & FLAG_EXTERNAL_TEST_MODE ? "on": "off",
648 devc->flag_reg & FLAG_RLE ? "on" : "off",
649 devc->flag_reg & FLAG_FILTER ? "on": "off",
650 devc->flag_reg & FLAG_DEMUX ? "on" : "off");
653 * Enable/disable OLS channel groups in the flag register according
654 * to the channel mask. 1 means "disable channel".
656 devc->flag_reg &= ~0x3c;
657 devc->flag_reg |= ~(pols_changrp_mask << 2) & 0x3c;
658 sr_dbg("flag_reg = %x", devc->flag_reg);
661 * In demux mode the OLS is processing two 8-bit or 16-bit samples
662 * in parallel and for this to work the lower two bits of the four
663 * "channel_disable" bits must be replicated to the upper two bits.
665 flag_tmp = devc->flag_reg;
666 if (devc->flag_reg & FLAG_DEMUX) {
668 flag_tmp |= ~(pols_changrp_mask << 4) & 0x30;
670 arg[0] = flag_tmp & 0xff;
671 arg[1] = flag_tmp >> 8;
672 arg[2] = arg[3] = 0x00;
673 if (write_longcommand(devc, CMD_SET_FLAGS, arg) != SR_OK)
676 /* Start acquisition on the device. */
677 if (write_shortcommand(devc, CMD_RUN) != SR_OK)
680 /* Reset all operational states. */
681 devc->rle_count = devc->num_transfers = 0;
682 devc->num_samples = devc->num_bytes = 0;
683 devc->cnt_bytes = devc->cnt_samples = devc->cnt_samples_rle = 0;
684 memset(devc->sample, 0, 4);
686 std_session_send_df_header(sdi, LOG_PREFIX);
688 /* Hook up a dummy handler to receive data from the device. */
689 sr_session_source_add(sdi->session, -1, 0, 10, p_ols_receive_data,
690 (struct sr_dev_inst *)sdi);
695 static int dev_acquisition_stop(struct sr_dev_inst *sdi)
697 struct dev_context *devc;
701 sr_dbg("Stopping acquisition.");
702 write_shortcommand(devc, CMD_RESET);
703 write_shortcommand(devc, CMD_RESET);
704 write_shortcommand(devc, CMD_RESET);
705 write_shortcommand(devc, CMD_RESET);
706 write_shortcommand(devc, CMD_RESET);
708 sr_session_source_remove(sdi->session, -1);
710 std_session_send_df_end(sdi, LOG_PREFIX);
715 SR_PRIV struct sr_dev_driver p_ols_driver_info = {
717 .longname = "Pipistrello OLS",
720 .cleanup = std_cleanup,
722 .dev_list = dev_list,
723 .dev_clear = dev_clear,
724 .config_get = config_get,
725 .config_set = config_set,
726 .config_list = config_list,
727 .dev_open = dev_open,
728 .dev_close = dev_close,
729 .dev_acquisition_start = dev_acquisition_start,
730 .dev_acquisition_stop = dev_acquisition_stop,