2 * This file is part of the libsigrok project.
4 * Copyright (C) 2015 Tilman Sauerbeck <tilman@code-monkey.de>
6 * This program is free software: you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation, either version 3 of the License, or
9 * (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program. If not, see <http://www.gnu.org/licenses/>.
25 #define EP_INTR (LIBUSB_ENDPOINT_IN | 1)
26 #define EP_BULK (LIBUSB_ENDPOINT_IN | 2)
27 #define EP_BITSTREAM (LIBUSB_ENDPOINT_OUT | 6)
29 #define CTRL_IN (LIBUSB_REQUEST_TYPE_VENDOR | LIBUSB_ENDPOINT_IN)
30 #define CTRL_OUT (LIBUSB_REQUEST_TYPE_VENDOR | LIBUSB_ENDPOINT_OUT)
32 #define USB_COMMAND_READ_WRITE_REGS 0xb1
33 #define USB_COMMAND_WRITE_STATUS_REG 0xb2
34 #define USB_COMMAND_START_UPLOAD 0xb3
35 #define USB_COMMAND_VERIFY_UPLOAD 0xb4
37 #define USB_TIMEOUT_MS 100
39 /* Firmware for acquisition on 8 channels. */
40 #define FPGA_FIRMWARE_8 "lecroy-logicstudio16-8.bitstream"
41 /* Firmware for acquisition on 16 channels. */
42 #define FPGA_FIRMWARE_16 "lecroy-logicstudio16-16.bitstream"
44 #define FPGA_FIRMWARE_SIZE 464196
45 #define FPGA_FIRMWARE_CHUNK_SIZE 2048
47 #define NUM_TRIGGER_STAGES 2
48 #define TRIGGER_CFG_SIZE 45
50 #define ALIGN2_DOWN(n, p) ((((n) > (p)) ? ((n) - (p)) : (n)) & ~((p) - 1))
52 #define TRIGGER_OP_A 0x1000
53 #define TRIGGER_OP_B 0x2000
54 #define TRIGGER_OP_A_OR_B 0x3000
55 #define TRIGGER_OP_A_AND_B 0x4000
56 #define TRIGGER_OP_A_THEN_B 0x8000
58 #define REG_ACQUISITION_ID 0x00
59 #define REG_SAMPLERATE 0x02
60 #define REG_PRETRIG_LO 0x03
61 #define REG_PRETRIG_HI 0x04
62 #define REG_POSTTRIG_LO 0x05
63 #define REG_POSTTRIG_HI 0x06
64 #define REG_ARM_TRIGGER 0x07
65 #define REG_FETCH_SAMPLES 0x08
66 #define REG_UNK1_LO 0x09
67 #define REG_UNK1_HI 0x0a
68 #define REG_UNK2_LO 0x0b
69 #define REG_UNK2_HI 0x0c
70 #define REG_UNK3_LO 0x0d
71 #define REG_UNK3_HI 0x0e
72 #define REG_UNK4_LO 0x0f
73 #define REG_UNK4_HI 0x10
74 #define REG_UNK5_LO 0x11
75 #define REG_UNK5_HI 0x12
76 #define REG_UNK6_LO 0x13
77 #define REG_UNK6_HI 0x14
78 #define REG_UNK0_LO 0x15
79 #define REG_UNK0_HI 0x16
80 #define REG_TRIGGER_CFG 0x18
81 #define REG_TRIGGER_COMBINE_OP 0x1b
82 #define REG_SELECT_CHANNELS 0x21
83 #define REG_VOLTAGE_THRESH_EXTERNAL 0x22
84 #define REG_VOLTAGE_THRESH_LOWER_CHANNELS 0x23
85 #define REG_VOLTAGE_THRESH_UPPER_CHANNELS 0x24
87 struct samplerate_info {
88 /** The samplerate in Hz. */
92 * The offset to add to the sample offset for when the trigger fired.
94 * @note The value stored here only applies to 8 channel mode.
95 * When acquiring 16 channels, subtract another 8 samples.
97 int8_t trigger_sample_offset;
102 struct trigger_config {
103 uint16_t rising_edges;
104 uint16_t falling_edges;
111 /** A register and its value. */
117 static void LIBUSB_CALL handle_fetch_samples_done(struct libusb_transfer *xfer);
118 static void LIBUSB_CALL recv_bulk_transfer(struct libusb_transfer *xfer);
120 static const struct samplerate_info samplerates[] = {
121 { SR_GHZ(1), -24, 0x1f },
122 { SR_MHZ(500), -6, 0x00 },
123 { SR_MHZ(250), -4, 0x01 },
124 { SR_MHZ(100), 2, 0x03 },
125 { SR_MHZ(50), 4, 0x04 },
126 { SR_MHZ(25), 8, 0x05 },
127 { SR_MHZ(10), 4, 0x07 },
128 { SR_MHZ(5), 8, 0x08 },
129 { SR_KHZ(2500), 8, 0x09 },
130 { SR_KHZ(1000), 8, 0x0b },
131 { SR_KHZ(500), 8, 0x0c },
132 { SR_KHZ(250), 8, 0x0d },
133 { SR_KHZ(100), 8, 0x0f },
134 { SR_KHZ(50), 8, 0x10 },
135 { SR_KHZ(25), 8, 0x11 },
136 { SR_KHZ(10), 8, 0x13 },
137 { SR_KHZ(5), 8, 0x14 },
138 { SR_HZ(2500), 8, 0x15 },
139 { SR_HZ(1000), 8, 0x17 },
142 static int read_register(const struct sr_dev_inst *sdi,
143 uint8_t reg, uint16_t *value)
145 struct sr_usb_dev_inst *usb;
151 r = libusb_control_transfer(usb->devhdl, CTRL_IN,
152 USB_COMMAND_READ_WRITE_REGS, reg, 5444,
153 data, sizeof(data), USB_TIMEOUT_MS);
155 if (r != sizeof(data)) {
156 sr_err("CTRL_IN failed: %i.", r);
165 static int write_registers_sync(const struct sr_dev_inst *sdi,
166 unsigned int wValue, unsigned int wIndex,
167 const struct regval *regs, size_t num_regs)
169 struct sr_usb_dev_inst *usb;
176 /* Try to avoid overflowing the stack. */
180 bufsiz = num_regs * 3;
181 buf = alloca(bufsiz);
183 for (i = 0; i < num_regs; i++) {
184 W8(&buf[i * 3 + 0], regs[i].reg);
185 WB16(&buf[i * 3 + 1], regs[i].val);
188 r = libusb_control_transfer(usb->devhdl, CTRL_OUT,
189 USB_COMMAND_READ_WRITE_REGS, wValue, wIndex,
190 buf, bufsiz, USB_TIMEOUT_MS);
192 if (r != (int) bufsiz) {
193 sr_err("write_registers_sync(%u/%u) failed.", wValue, wIndex);
200 static int write_registers_async(const struct sr_dev_inst *sdi,
201 unsigned int wValue, unsigned int wIndex,
202 const struct regval *regs, size_t num_regs,
203 libusb_transfer_cb_fn callback)
205 struct sr_usb_dev_inst *usb;
206 struct libusb_transfer *xfer;
207 uint8_t *buf, *xfer_buf;
212 xfer = libusb_alloc_transfer(0);
213 xfer_buf = g_malloc(LIBUSB_CONTROL_SETUP_SIZE + (num_regs * 3));
215 libusb_fill_control_setup(xfer_buf, CTRL_OUT,
216 USB_COMMAND_READ_WRITE_REGS, wValue, wIndex, num_regs * 3);
218 buf = xfer_buf + LIBUSB_CONTROL_SETUP_SIZE;
220 for (i = 0; i < num_regs; i++) {
221 W8(&buf[i * 3 + 0], regs[i].reg);
222 WB16(&buf[i * 3 + 1], regs[i].val);
225 libusb_fill_control_transfer(xfer, usb->devhdl,
226 xfer_buf, callback, (void *) sdi, USB_TIMEOUT_MS);
228 if (libusb_submit_transfer(xfer) < 0) {
229 g_free(xfer->buffer);
231 libusb_free_transfer(xfer);
238 static void prep_regw(struct regval *regval, uint8_t reg, uint16_t val)
244 static void LIBUSB_CALL handle_fetch_samples_done(struct libusb_transfer *xfer)
246 const struct sr_dev_inst *sdi;
247 struct sr_usb_dev_inst *usb;
248 struct dev_context *devc;
250 sdi = xfer->user_data;
254 g_free(xfer->buffer);
257 libusb_free_transfer(xfer);
259 libusb_fill_bulk_transfer(devc->bulk_xfer, usb->devhdl, EP_BULK,
260 devc->fetched_samples, 17 << 10,
261 recv_bulk_transfer, (void *)sdi, USB_TIMEOUT_MS);
263 libusb_submit_transfer(devc->bulk_xfer);
266 static void calc_unk0(uint32_t *a, uint32_t *b)
278 static int fetch_samples_async(const struct sr_dev_inst *sdi)
280 struct dev_context *devc;
281 struct regval cmd[12];
282 uint32_t unk1, unk2, unk3;
287 unk1 = devc->earliest_sample % (devc->num_thousand_samples << 10);
288 unk1 = (unk1 * devc->num_enabled_channel_groups) / 8;
290 calc_unk0(&unk2, &unk3);
294 prep_regw(&cmd[i++], REG_UNK1_LO, (unk1 >> 0) & 0xffff);
295 prep_regw(&cmd[i++], REG_UNK1_HI, (unk1 >> 16) & 0xffff);
297 prep_regw(&cmd[i++], REG_FETCH_SAMPLES, devc->magic_fetch_samples);
298 prep_regw(&cmd[i++], REG_FETCH_SAMPLES, devc->magic_fetch_samples | 0x02);
300 prep_regw(&cmd[i++], REG_UNK1_LO, 0x0000);
301 prep_regw(&cmd[i++], REG_UNK1_HI, 0x0000);
303 prep_regw(&cmd[i++], REG_UNK2_LO, (unk2 >> 0) & 0xffff);
304 prep_regw(&cmd[i++], REG_UNK2_HI, (unk2 >> 16) & 0xffff);
306 prep_regw(&cmd[i++], REG_UNK3_LO, (unk3 >> 0) & 0xffff);
307 prep_regw(&cmd[i++], REG_UNK3_HI, (unk3 >> 16) & 0xffff);
309 devc->magic_fetch_samples = 0x01;
310 prep_regw(&cmd[i++], REG_FETCH_SAMPLES, devc->magic_fetch_samples + 0x01);
311 prep_regw(&cmd[i++], REG_FETCH_SAMPLES, devc->magic_fetch_samples | 0x02);
313 return write_registers_async(sdi, 0x12, 5444, cmd, ARRAY_SIZE(cmd),
314 handle_fetch_samples_done);
317 static int handle_intr_data(const struct sr_dev_inst *sdi, uint8_t *buffer)
319 struct dev_context *devc;
320 gboolean resubmit_intr_xfer;
321 uint64_t time_latest, time_trigger, sample_latest, sample_trigger;
322 uint32_t samplerate_divider;
324 resubmit_intr_xfer = TRUE;
331 if (!devc->want_trigger)
334 /* Does this packet refer to our newly programmed trigger yet? */
335 if (RB16(&buffer[0x02]) != devc->acquisition_id)
338 switch (buffer[0x1f]) {
340 /* Storing pre-trigger samples. */
346 /* Storing post-trigger samples. */
349 /* Acquisition complete. */
350 devc->total_received_sample_bytes = 0;
352 samplerate_divider = SR_GHZ(1) / devc->samplerate_info->samplerate;
355 * These timestamps seem to be in units of eight nanoseconds.
356 * The first one refers to the time when the latest sample
357 * was written to the device's sample buffer, and the second
358 * one refers to the time when the trigger fired.
360 * They are stored as 48 bit integers in the packet and we
361 * shift it to the right by 16 to make up for that.
363 time_latest = RB64(&buffer[0x6]) >> 16;
364 time_trigger = RB64(&buffer[0xc]) >> 16;
366 /* Convert timestamps to sample offsets. */
367 sample_latest = time_latest * 8;
368 sample_latest /= samplerate_divider;
370 sample_latest = ALIGN2_DOWN(sample_latest,
371 8 / devc->num_enabled_channel_groups);
373 devc->earliest_sample = sample_latest -
374 (devc->num_thousand_samples * 1000);
376 sample_trigger = time_trigger * 8;
378 /* Fill the zero bits on the right. */
379 sample_trigger |= RB16(&buffer[0x12]) & 7;
381 sample_trigger += devc->samplerate_info->trigger_sample_offset;
383 if (devc->num_enabled_channel_groups > 1)
386 sample_trigger -= 0x18;
388 if (samplerate_divider > 1) {
389 /* FIXME: Underflow. */
390 sample_trigger -= samplerate_divider;
391 sample_trigger /= samplerate_divider;
395 * Seems the hardware reports one sample too early,
396 * so make up for that.
400 devc->trigger_sample = sample_trigger;
402 fetch_samples_async(sdi);
405 * Don't re-submit the interrupt transfer;
406 * we need to get the samples instead.
408 resubmit_intr_xfer = FALSE;
416 return resubmit_intr_xfer;
419 static int upload_fpga_bitstream(const struct sr_dev_inst *sdi,
420 const char *firmware_name)
422 struct drv_context *drvc;
423 struct sr_usb_dev_inst *usb;
424 struct sr_resource firmware;
425 uint8_t firmware_chunk[FPGA_FIRMWARE_CHUNK_SIZE];
426 uint8_t upload_succeeded;
428 int i, r, ret, actual_length;
430 drvc = sdi->driver->context;
433 ret = sr_resource_open(drvc->sr_ctx, &firmware,
434 SR_RESOURCE_FIRMWARE, firmware_name);
441 if (firmware.size != FPGA_FIRMWARE_SIZE) {
442 sr_err("Invalid FPGA firmware file size: %" PRIu64 " bytes.",
447 /* Initiate upload. */
448 r = libusb_control_transfer(usb->devhdl, CTRL_OUT,
449 USB_COMMAND_START_UPLOAD, 0x07, 5444,
450 NULL, 0, USB_TIMEOUT_MS);
453 sr_err("Failed to initiate firmware upload: %s.",
454 libusb_error_name(ret));
459 chunk_size = sr_resource_read(drvc->sr_ctx, &firmware,
460 firmware_chunk, sizeof(firmware_chunk));
468 actual_length = chunk_size;
470 r = libusb_bulk_transfer(usb->devhdl, EP_BITSTREAM,
471 firmware_chunk, chunk_size, &actual_length, USB_TIMEOUT_MS);
473 if (r != 0 || (ssize_t)actual_length != chunk_size) {
474 sr_err("FPGA firmware upload failed.");
480 for (i = 0; i < 4; i++) {
483 upload_succeeded = 0x00;
485 r = libusb_control_transfer(usb->devhdl, CTRL_IN,
486 USB_COMMAND_VERIFY_UPLOAD, 0x07, 5444,
487 &upload_succeeded, sizeof(upload_succeeded),
490 if (r != sizeof(upload_succeeded)) {
491 sr_err("CTRL_IN failed: %i.", r);
495 if (upload_succeeded == 0x01) {
502 sr_resource_close(drvc->sr_ctx, &firmware);
507 static int upload_trigger(const struct sr_dev_inst *sdi,
508 uint8_t reg_values[TRIGGER_CFG_SIZE], uint8_t reg_offset)
510 struct regval regs[3 * 5];
514 for (i = 0; i < TRIGGER_CFG_SIZE; i += 5) {
517 for (j = 0; j < 5; j++) {
518 value = ((reg_offset + i + j) << 8) | reg_values[i + j];
520 prep_regw(®s[k++], REG_TRIGGER_CFG, value);
521 prep_regw(®s[k++], REG_TRIGGER_CFG, value | 0x8000);
522 prep_regw(®s[k++], REG_TRIGGER_CFG, value);
525 if (write_registers_sync(sdi, 0x12, 5444, regs, ARRAY_SIZE(regs))) {
526 sr_err("Failed to upload trigger config.");
534 static int program_trigger(const struct sr_dev_inst *sdi,
535 struct trigger_config *stages, int num_filled_stages)
537 struct trigger_config *block;
538 struct regval combine_op;
539 uint8_t buf[TRIGGER_CFG_SIZE];
540 const uint8_t reg_offsets[] = { 0x00, 0x40 };
543 for (i = 0; i < NUM_TRIGGER_STAGES; i++) {
546 memset(buf, 0, sizeof(buf));
548 WL16(&buf[0x00], ~(block->rising_edges | block->falling_edges));
549 WL16(&buf[0x05], block->rising_edges | block->falling_edges | block->any_edges);
551 if (block->ones | block->zeroes)
554 WL16(&buf[0x0a], block->rising_edges);
555 WL16(&buf[0x0f], block->ones | block->zeroes);
557 WL16(&buf[0x14], block->ones | 0x8000);
559 if (block->ones == 0x01)
560 WL16(&buf[0x19], block->ones << 1);
562 WL16(&buf[0x19], block->ones | 0x0001);
565 * The final trigger has some special stuff.
566 * Not sure of the meaning yet.
568 if (i == NUM_TRIGGER_STAGES - 1) {
569 buf[0x09] = 0x10; /* This is most likely wrong. */
578 if (upload_trigger(sdi, buf, reg_offsets[i]) < 0)
583 * If both available stages are used, AND them in the trigger
586 * Once sigrok learns to teach devices about the combination
587 * that the user wants, this seems to be the best default since
588 * edge triggers cannot be AND'ed otherwise
589 * (they are always OR'd within a single stage).
591 prep_regw(&combine_op, REG_TRIGGER_COMBINE_OP,
592 num_filled_stages > 1 ? TRIGGER_OP_A_AND_B : TRIGGER_OP_A);
594 return write_registers_sync(sdi, 0x12, 5444, &combine_op, 1);
597 static gboolean transform_trigger(struct sr_trigger_stage *stage,
598 struct trigger_config *config)
601 struct sr_trigger_match *match;
602 uint32_t channel_mask;
607 for (l = stage->matches; l; l = l->next) {
613 /* Ignore disabled channels. */
614 if (!match->channel->enabled)
617 channel_mask = 1 << match->channel->index;
619 switch (match->match) {
620 case SR_TRIGGER_RISING:
621 config->rising_edges |= channel_mask;
623 case SR_TRIGGER_FALLING:
624 config->falling_edges |= channel_mask;
626 case SR_TRIGGER_EDGE:
627 config->any_edges |= channel_mask;
630 config->ones |= channel_mask;
632 case SR_TRIGGER_ZERO:
633 config->zeroes |= channel_mask;
643 static int configure_trigger(const struct sr_dev_inst *sdi)
645 struct dev_context *devc;
646 struct sr_trigger *trigger;
647 struct sr_trigger_stage *stage;
648 struct sr_trigger_match *match;
649 struct trigger_config blocks[NUM_TRIGGER_STAGES];
650 gboolean stage_has_matches;
651 int num_filled_stages;
656 trigger = sr_session_trigger_get(sdi->session);
658 num_filled_stages = 0;
660 memset(blocks, 0, sizeof(blocks));
662 for (l = trigger ? trigger->stages : NULL; l; l = l->next) {
664 stage_has_matches = FALSE;
666 /* Check if this stage has any interesting matches. */
667 for (ll = stage->matches; ll; ll = ll->next) {
673 /* Ignore disabled channels. */
674 if (match->channel->enabled) {
675 stage_has_matches = TRUE;
680 if (stage_has_matches == FALSE)
683 if (num_filled_stages == NUM_TRIGGER_STAGES)
686 if (transform_trigger(stage, &blocks[num_filled_stages]))
690 devc->want_trigger = num_filled_stages > 0;
692 return program_trigger(sdi, blocks, num_filled_stages);
695 /** Update the bit mask of enabled channels. */
696 SR_PRIV void lls_update_channel_mask(const struct sr_dev_inst *sdi)
698 struct dev_context *devc;
699 struct sr_channel *channel;
704 devc->channel_mask = 0;
706 for (l = sdi->channels; l; l = l->next) {
708 if (channel->enabled)
709 devc->channel_mask |= 1 << channel->index;
713 SR_PRIV int lls_set_samplerate(const struct sr_dev_inst *sdi,
716 struct dev_context *devc;
721 for (i = 0; i < ARRAY_SIZE(samplerates); i++) {
722 if (samplerates[i].samplerate == samplerate) {
723 devc->samplerate_info = &samplerates[i];
731 SR_PRIV uint64_t lls_get_samplerate(const struct sr_dev_inst *sdi)
733 struct dev_context *devc;
737 return devc->samplerate_info->samplerate;
740 static int read_0f12(const struct sr_dev_inst *sdi, uint64_t *value)
749 * Read the 64 bit register spread over 4 16 bit registers.
751 * Note that these don't seem to be the same registers we're writing
752 * when arming the trigger (ie REG_UNK4 and REG_UNK5).
753 * Seems there's multiple register spaces?
755 for (reg = 0x0f; reg <= 0x12; reg++) {
756 r = read_register(sdi, reg, &u16);
768 static int wait_for_dev_to_settle(const struct sr_dev_inst *sdi)
770 uint64_t old_value, new_value;
773 /* Get the initial value. */
774 r = read_0f12(sdi, &old_value);
780 * We are looking for two consecutive reads that yield the
781 * same value. Try a couple of times.
783 for (i = 0; i < 100; i++) {
784 r = read_0f12(sdi, &new_value);
788 if (old_value == new_value)
791 old_value = new_value;
797 SR_PRIV int lls_setup_acquisition(const struct sr_dev_inst *sdi)
799 uint8_t status_reg_value[] = {
800 0x1, 0x0, 0x7, 0x8, 0x9, 0xa, 0xb, 0xc,
801 0xd, 0xe, 0x1, 0x2, 0x3, 0x4, 0x5, 0x6
803 struct regval threshold[3];
804 struct regval channels;
805 struct dev_context *devc;
806 struct sr_usb_dev_inst *usb;
807 gboolean lower_enabled, upper_enabled, upload_bitstream;
808 uint32_t num_thousand_samples, num_enabled_channel_groups;
814 prep_regw(&threshold[0], REG_VOLTAGE_THRESH_LOWER_CHANNELS, 0x00c3);
815 prep_regw(&threshold[1], REG_VOLTAGE_THRESH_UPPER_CHANNELS, 0x00c2);
816 prep_regw(&threshold[2], REG_VOLTAGE_THRESH_EXTERNAL, 0x003e);
818 lls_update_channel_mask(sdi);
820 lower_enabled = (devc->channel_mask & 0x00ff) != 0x00;
821 upper_enabled = (devc->channel_mask & 0xff00) != 0x00;
823 num_thousand_samples = 20;
824 num_enabled_channel_groups = 2;
826 if (lower_enabled != upper_enabled) {
827 num_thousand_samples <<= 1;
828 num_enabled_channel_groups >>= 1;
831 if (upper_enabled && !lower_enabled)
832 prep_regw(&channels, REG_SELECT_CHANNELS, 0x01);
834 prep_regw(&channels, REG_SELECT_CHANNELS, 0x00);
837 * If the number of enabled channel groups changed since
838 * the last acquisition, we need to switch FPGA bitstreams.
839 * This works for the initial bitstream upload because
840 * devc->num_enabled_channel_groups is initialized to zero.
843 devc->num_enabled_channel_groups != num_enabled_channel_groups;
845 if (upload_bitstream) {
846 if (lls_stop_acquisition(sdi)) {
847 sr_err("Cannot stop acquisition for FPGA bitstream upload.");
851 for (i = 0; i < 3; i++)
852 if (write_registers_sync(sdi, 0x0, 0x0, &threshold[i], 1))
855 if (num_enabled_channel_groups == 1)
856 r = upload_fpga_bitstream(sdi, FPGA_FIRMWARE_8);
858 r = upload_fpga_bitstream(sdi, FPGA_FIRMWARE_16);
861 sr_err("Firmware not accepted by device.");
865 r = wait_for_dev_to_settle(sdi);
868 sr_err("Device did not settle in time.");
872 for (i = 0; i < 3; i++)
873 if (write_registers_sync(sdi, 0x12, 5444, &threshold[i], 1))
876 devc->magic_arm_trigger = 0x00;
877 devc->magic_fetch_samples = 0x00;
880 if (write_registers_sync(sdi, 0x12, 5444, &channels, 1))
883 if (configure_trigger(sdi) < 0)
886 if (write_registers_sync(sdi, 0x12, 5444, &threshold[0], 1))
889 if (write_registers_sync(sdi, 0x12, 5444, &threshold[1], 1))
892 if (upload_bitstream) {
893 r = libusb_control_transfer(usb->devhdl, CTRL_OUT,
894 USB_COMMAND_WRITE_STATUS_REG, 0x12, 5444,
895 status_reg_value, sizeof(status_reg_value), USB_TIMEOUT_MS);
897 if (r != sizeof(status_reg_value)) {
898 sr_err("Failed to write status register: %s.",
899 libusb_error_name(r));
904 devc->num_thousand_samples = num_thousand_samples;
905 devc->num_enabled_channel_groups = num_enabled_channel_groups;
910 static void LIBUSB_CALL recv_intr_transfer(struct libusb_transfer *xfer)
912 const struct sr_dev_inst *sdi;
913 struct drv_context *drvc;
914 struct dev_context *devc;
916 sdi = xfer->user_data;
917 drvc = sdi->driver->context;
920 if (devc->abort_acquisition) {
921 std_session_send_df_end(sdi);
922 usb_source_remove(sdi->session, drvc->sr_ctx);
926 if (xfer->status == LIBUSB_TRANSFER_COMPLETED) {
927 if (xfer->actual_length != INTR_BUF_SIZE)
928 sr_err("Invalid size of interrupt transfer: %u.",
929 xfer->actual_length);
930 else if (handle_intr_data(sdi, xfer->buffer)) {
931 if (libusb_submit_transfer(xfer) < 0)
932 sr_err("Failed to submit interrupt transfer.");
937 static void send_samples(const struct sr_dev_inst *sdi,
938 uint8_t *samples, uint32_t length)
940 struct dev_context *devc;
941 struct sr_datafeed_packet packet;
942 struct sr_datafeed_logic logic;
943 gboolean lower_enabled, upper_enabled;
948 lower_enabled = (devc->channel_mask & 0x00ff) != 0x00;
949 upper_enabled = (devc->channel_mask & 0xff00) != 0x00;
953 packet.type = SR_DF_LOGIC;
954 packet.payload = &logic;
956 if (lower_enabled && upper_enabled) {
957 logic.length = length;
958 logic.data = samples;
960 sr_session_send(sdi, &packet);
962 /* Which channel group is enabled? */
963 shift = (lower_enabled) ? 0 : 8;
965 while (length >= (CONV_8TO16_BUF_SIZE / 2)) {
966 for (i = 0; i < (CONV_8TO16_BUF_SIZE / 2); i++) {
967 devc->conv8to16[i] = samples[i];
968 devc->conv8to16[i] <<= shift;
971 logic.length = CONV_8TO16_BUF_SIZE;
972 logic.data = devc->conv8to16;
974 sr_session_send(sdi, &packet);
976 samples += CONV_8TO16_BUF_SIZE / 2;
977 length -= CONV_8TO16_BUF_SIZE / 2;
980 /* Handle the remaining samples. */
981 for (i = 0; i < length; i++) {
982 devc->conv8to16[i] = samples[i];
983 devc->conv8to16[i] <<= shift;
986 logic.length = length * 2;
987 logic.data = devc->conv8to16;
989 sr_session_send(sdi, &packet);
993 static uint16_t sample_to_byte_offset(struct dev_context *devc, uint64_t o)
995 o %= devc->num_thousand_samples << 10;
997 /* We have 8 bit per channel group, so this gets us a byte offset. */
998 return o * devc->num_enabled_channel_groups;
1001 static void LIBUSB_CALL recv_bulk_transfer(struct libusb_transfer *xfer)
1003 const struct sr_dev_inst *sdi;
1004 struct dev_context *devc;
1005 struct drv_context *drvc;
1006 struct sr_datafeed_packet packet;
1007 uint32_t bytes_left, length;
1008 uint16_t read_offset, trigger_offset;
1010 sdi = xfer->user_data;
1015 drvc = sdi->driver->context;
1018 devc->total_received_sample_bytes += xfer->actual_length;
1020 if (devc->total_received_sample_bytes < SAMPLE_BUF_SIZE) {
1021 xfer->buffer = devc->fetched_samples
1022 + devc->total_received_sample_bytes;
1024 xfer->length = MIN(16 << 10,
1025 SAMPLE_BUF_SIZE - devc->total_received_sample_bytes);
1027 libusb_submit_transfer(xfer);
1031 usb_source_remove(sdi->session, drvc->sr_ctx);
1033 read_offset = sample_to_byte_offset(devc, devc->earliest_sample);
1034 trigger_offset = sample_to_byte_offset(devc, devc->trigger_sample);
1037 * The last few bytes seem to contain garbage data,
1040 bytes_left = (SAMPLE_BUF_SIZE >> 10) * 1000;
1042 sr_spew("Start reading at offset 0x%04hx.", read_offset);
1043 sr_spew("Trigger offset 0x%04hx.", trigger_offset);
1045 if (trigger_offset < read_offset) {
1046 length = MIN(bytes_left, SAMPLE_BUF_SIZE - read_offset);
1048 sr_spew("Sending %u pre-trigger bytes starting at 0x%04hx.",
1049 length, read_offset);
1051 send_samples(sdi, &devc->fetched_samples[read_offset], length);
1053 bytes_left -= length;
1058 length = MIN(bytes_left, (uint32_t)(trigger_offset - read_offset));
1060 sr_spew("Sending %u pre-trigger bytes starting at 0x%04hx.",
1061 length, read_offset);
1063 send_samples(sdi, &devc->fetched_samples[read_offset], length);
1065 bytes_left -= length;
1067 read_offset += length;
1068 read_offset %= SAMPLE_BUF_SIZE;
1071 /* Here comes the trigger. */
1072 packet.type = SR_DF_TRIGGER;
1073 packet.payload = NULL;
1075 sr_session_send(sdi, &packet);
1077 /* Send post-trigger samples. */
1078 while (bytes_left > 0) {
1079 length = MIN(bytes_left, SAMPLE_BUF_SIZE - read_offset);
1081 sr_spew("Sending %u post-trigger bytes starting at 0x%04hx.",
1082 length, read_offset);
1084 send_samples(sdi, &devc->fetched_samples[read_offset], length);
1086 bytes_left -= length;
1088 read_offset += length;
1089 read_offset %= SAMPLE_BUF_SIZE;
1092 std_session_send_df_end(sdi);
1095 static uint32_t transform_sample_count(struct dev_context *devc,
1098 uint32_t d = 8 / devc->num_enabled_channel_groups;
1100 return (samples + 0x1c + d + d - 1) / d;
1103 SR_PRIV int lls_start_acquisition(const struct sr_dev_inst *sdi)
1105 struct sr_usb_dev_inst *usb;
1106 struct dev_context *devc;
1107 struct regval cmd[17];
1108 uint32_t unk0, total_samples, pre_trigger_samples, post_trigger_samples;
1109 uint32_t pre_trigger_tr, post_trigger_tr;
1115 devc->abort_acquisition = FALSE;
1117 libusb_fill_interrupt_transfer(devc->intr_xfer, usb->devhdl, EP_INTR,
1118 devc->intr_buf, INTR_BUF_SIZE,
1119 recv_intr_transfer, (void *) sdi, USB_TIMEOUT_MS);
1121 libusb_submit_transfer(devc->intr_xfer);
1123 if (devc->want_trigger == FALSE)
1126 calc_unk0(&unk0, NULL);
1128 total_samples = devc->num_thousand_samples * 1000;
1130 pre_trigger_samples = total_samples * devc->capture_ratio / 100;
1131 post_trigger_samples = total_samples - pre_trigger_samples;
1133 pre_trigger_tr = transform_sample_count(devc, pre_trigger_samples);
1134 post_trigger_tr = transform_sample_count(devc, post_trigger_samples);
1138 prep_regw(&cmd[i++], REG_ARM_TRIGGER, devc->magic_arm_trigger);
1139 prep_regw(&cmd[i++], REG_ARM_TRIGGER, devc->magic_arm_trigger | 0x02);
1141 prep_regw(&cmd[i++], REG_UNK6_LO, 0x0000);
1142 prep_regw(&cmd[i++], REG_UNK6_HI, 0x0000);
1144 prep_regw(&cmd[i++], REG_UNK0_LO, (unk0 >> 0) & 0xffff);
1145 prep_regw(&cmd[i++], REG_UNK0_HI, (unk0 >> 16) & 0xffff);
1147 prep_regw(&cmd[i++], REG_UNK4_LO, 0x0000);
1148 prep_regw(&cmd[i++], REG_UNK4_HI, 0x0000);
1150 prep_regw(&cmd[i++], REG_UNK5_LO, 0x0000);
1151 prep_regw(&cmd[i++], REG_UNK5_HI, 0x0000);
1153 prep_regw(&cmd[i++], REG_ACQUISITION_ID, ++devc->acquisition_id);
1154 prep_regw(&cmd[i++], REG_SAMPLERATE, devc->samplerate_info->cfg);
1156 prep_regw(&cmd[i++], REG_PRETRIG_LO, (pre_trigger_tr >> 0) & 0xffff);
1157 prep_regw(&cmd[i++], REG_PRETRIG_HI, (pre_trigger_tr >> 16) & 0xffff);
1159 prep_regw(&cmd[i++], REG_POSTTRIG_LO, (post_trigger_tr >> 0) & 0xffff);
1160 prep_regw(&cmd[i++], REG_POSTTRIG_HI, (post_trigger_tr >> 16) & 0xffff);
1162 devc->magic_arm_trigger = 0x0c;
1163 prep_regw(&cmd[i++], REG_ARM_TRIGGER, devc->magic_arm_trigger | 0x01);
1165 return write_registers_sync(sdi, 0x12, 5444, cmd, ARRAY_SIZE(cmd));
1168 SR_PRIV int lls_stop_acquisition(const struct sr_dev_inst *sdi)
1170 struct dev_context *devc;
1171 struct regval cmd[2];
1176 devc->abort_acquisition = TRUE;
1180 prep_regw(&cmd[i++], REG_ARM_TRIGGER, devc->magic_arm_trigger);
1181 prep_regw(&cmd[i++], REG_ARM_TRIGGER, devc->magic_arm_trigger | 0x02);
1183 assert(i == ARRAY_SIZE(cmd));
1185 return write_registers_sync(sdi, 0x12, 5444, cmd, ARRAY_SIZE(cmd));