2 * This file is part of the libsigrok project.
4 * Copyright (C) 2022 Gerhard Sittig <gerhard.sittig@gmx.net>
5 * Copyright (C) 2020 Florian Schmidt <schmidt_florian@gmx.de>
6 * Copyright (C) 2013 Marcus Comstedt <marcus@mc.pp.se>
7 * Copyright (C) 2013 Bert Vermeulen <bert@biot.com>
8 * Copyright (C) 2012 Joel Holdsworth <joel@airwebreathe.org.uk>
10 * This program is free software: you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation, either version 3 of the License, or
13 * (at your option) any later version.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program. If not, see <http://www.gnu.org/licenses/>.
26 #include <libsigrok/libsigrok.h>
29 #include "libsigrok-internal.h"
32 /* USB PID dependent MCU firmware. Model dependent FPGA bitstream. */
33 #define MCU_FWFILE_FMT "kingst-la-%04x.fw"
34 #define FPGA_FWFILE_FMT "kingst-%s-fpga.bitstream"
37 * List of supported devices and their features. See @ref kingst_model
38 * for the fields' type and meaning. Table is sorted by EEPROM magic.
41 * - Below LA1016 properties were guessed, need verification.
42 * - Add LA5016 and LA5032 devices when their EEPROM magic is known.
43 * - Does LA1010 fit the driver implementation? Samplerates vary with
44 * channel counts, lack of local sample memory. Most probably not.
46 static const struct kingst_model models[] = {
47 { 2, "LA2016", "la2016", SR_MHZ(200), 16, 1, },
48 { 3, "LA1016", "la1016", SR_MHZ(100), 16, 1, },
49 { 8, "LA2016", "la2016a1", SR_MHZ(200), 16, 1, },
50 { 9, "LA1016", "la1016a1", SR_MHZ(100), 16, 1, },
53 /* USB vendor class control requests, executed by the Cypress FX2 MCU. */
54 #define CMD_FPGA_ENABLE 0x10
55 #define CMD_FPGA_SPI 0x20 /* R/W access to FPGA registers via SPI. */
56 #define CMD_BULK_START 0x30 /* Start sample data download via USB EP6 IN. */
57 #define CMD_BULK_RESET 0x38 /* Flush FIFO of FX2 USB EP6 IN. */
58 #define CMD_FPGA_INIT 0x50 /* Used before and after FPGA bitstream upload. */
59 #define CMD_KAUTH 0x60 /* Communicate to auth IC (U10). Not used. */
60 #define CMD_EEPROM 0xa2 /* R/W access to EEPROM content. */
63 * FPGA register addresses (base addresses when registers span multiple
64 * bytes, in that case data is kept in little endian format). Passed to
65 * CMD_FPGA_SPI requests. The FX2 MCU transparently handles the detail
66 * of SPI transfers encoding the read (1) or write (0) direction in the
67 * MSB of the address field. There are some 60 byte-wide FPGA registers.
69 * Unfortunately the FPGA registers change their meaning between the
70 * read and write directions of access, or exclusively provide one of
71 * these directions and not the other. This is an arbitrary vendor's
72 * choice, there is nothing which the sigrok driver could do about it.
73 * Values written to registers typically cannot get read back, neither
74 * verified after writing a configuration, nor queried upon startup for
75 * automatic detection of the current configuration. Neither appear to
76 * be there echo registers for presence and communication checks, nor
77 * version identifying registers, as far as we know.
79 #define REG_RUN 0x00 /* Read capture status, write start capture. */
80 #define REG_PWM_EN 0x02 /* User PWM channels on/off. */
81 #define REG_CAPT_MODE 0x03 /* Write 0x00 capture to SDRAM, 0x01 streaming. */
82 #define REG_PIN_STATE 0x04 /* Read current pin state (real time display). */
83 #define REG_BULK 0x08 /* Write start addr, byte count to download samples. */
84 #define REG_SAMPLING 0x10 /* Write capture config, read capture SDRAM location. */
85 #define REG_TRIGGER 0x20 /* Write level and edge trigger config. */
86 #define REG_UNKNOWN_30 0x30
87 #define REG_THRESHOLD 0x68 /* Write PWM config to setup input threshold DAC. */
88 #define REG_PWM1 0x70 /* Write config for user PWM1. */
89 #define REG_PWM2 0x78 /* Write config for user PWM2. */
91 /* Bit patterns to write to REG_CAPT_MODE. */
92 #define CAPTMODE_TO_RAM 0x00
93 #define CAPTMODE_STREAM 0x01
95 /* Bit patterns to write to REG_RUN, setup run mode. */
96 #define RUNMODE_HALT 0x00
97 #define RUNMODE_RUN 0x03
99 /* Bit patterns when reading from REG_RUN, get run state. */
100 #define RUNSTATE_IDLE_BIT (1UL << 0)
101 #define RUNSTATE_DRAM_BIT (1UL << 1)
102 #define RUNSTATE_TRGD_BIT (1UL << 2)
103 #define RUNSTATE_POST_BIT (1UL << 3)
105 static int ctrl_in(const struct sr_dev_inst *sdi,
106 uint8_t bRequest, uint16_t wValue, uint16_t wIndex,
107 void *data, uint16_t wLength)
109 struct sr_usb_dev_inst *usb;
114 ret = libusb_control_transfer(usb->devhdl,
115 LIBUSB_REQUEST_TYPE_VENDOR | LIBUSB_ENDPOINT_IN,
116 bRequest, wValue, wIndex, data, wLength,
118 if (ret != wLength) {
119 sr_dbg("USB ctrl in: %d bytes, req %d val %#x idx %d: %s.",
120 wLength, bRequest, wValue, wIndex,
121 libusb_error_name(ret));
122 sr_err("Cannot read %d bytes from USB: %s.",
123 wLength, libusb_error_name(ret));
130 static int ctrl_out(const struct sr_dev_inst *sdi,
131 uint8_t bRequest, uint16_t wValue, uint16_t wIndex,
132 void *data, uint16_t wLength)
134 struct sr_usb_dev_inst *usb;
139 ret = libusb_control_transfer(usb->devhdl,
140 LIBUSB_REQUEST_TYPE_VENDOR | LIBUSB_ENDPOINT_OUT,
141 bRequest, wValue, wIndex, data, wLength,
143 if (ret != wLength) {
144 sr_dbg("USB ctrl out: %d bytes, req %d val %#x idx %d: %s.",
145 wLength, bRequest, wValue, wIndex,
146 libusb_error_name(ret));
147 sr_err("Cannot write %d bytes to USB: %s.",
148 wLength, libusb_error_name(ret));
155 /* HACK Experiment to spot FPGA registers of interest. */
156 static void la2016_dump_fpga_registers(const struct sr_dev_inst *sdi,
157 const char *caption, size_t reg_lower, size_t reg_upper)
159 static const size_t dump_chunk_len = 16;
162 uint8_t rdbuf[0x80 - 0x00]; /* Span all FPGA registers. */
163 const uint8_t *rdptr;
165 size_t dump_addr, indent, dump_len;
168 if (sr_log_loglevel_get() < SR_LOG_SPEW)
171 if (!reg_lower && !reg_upper) {
173 reg_upper = sizeof(rdbuf);
175 if (reg_upper - reg_lower > sizeof(rdbuf))
176 reg_upper = sizeof(rdbuf) - reg_lower;
178 rdlen = reg_upper - reg_lower;
179 ret = ctrl_in(sdi, CMD_FPGA_SPI, reg_lower, 0, rdbuf, rdlen);
181 sr_err("Cannot get registers space.");
186 sr_spew("FPGA registers dump: %s", caption ? : "for fun");
187 dump_addr = reg_lower;
190 indent = dump_addr % dump_chunk_len;
191 if (dump_len > dump_chunk_len)
192 dump_len = dump_chunk_len;
193 if (dump_len + indent > dump_chunk_len)
194 dump_len = dump_chunk_len - indent;
195 txt = sr_hexdump_new(rdptr, dump_len);
196 sr_spew(" %04zx %*s%s",
197 dump_addr, (int)(3 * indent), "", txt->str);
198 sr_hexdump_free(txt);
199 dump_addr += dump_len;
206 * Check the necessity for FPGA bitstream upload, because another upload
207 * would take some 600ms which is undesirable after program startup. Try
208 * to access some FPGA registers and check the values' plausibility. The
209 * check should fail on the safe side, request another upload when in
210 * doubt. A positive response (the request to continue operation with the
211 * currently active bitstream) should be conservative. Accessing multiple
212 * registers is considered cheap compared to the cost of bitstream upload.
214 * It helps though that both the vendor software and the sigrok driver
215 * use the same bundle of MCU firmware and FPGA bitstream for any of the
216 * supported models. We don't expect to successfully communicate to the
217 * device yet disagree on its protocol. Ideally we would access version
218 * identifying registers for improved robustness, but are not aware of
219 * any. A bitstream reload can always be forced by a power cycle.
221 static int check_fpga_bitstream(const struct sr_dev_inst *sdi)
224 uint8_t buff[REG_PWM_EN - REG_RUN]; /* Larger of REG_RUN, REG_PWM_EN. */
229 const uint8_t *rdptr;
231 sr_dbg("Checking operation of the FPGA bitstream.");
232 la2016_dump_fpga_registers(sdi, "bitstream check", 0, 0);
235 ret = ctrl_in(sdi, CMD_FPGA_INIT, 0x00, 0, &init_rsp, sizeof(init_rsp));
236 if (ret != SR_OK || init_rsp != 0) {
237 sr_dbg("FPGA init query failed, or unexpected response.");
241 read_len = sizeof(run_state);
242 ret = ctrl_in(sdi, CMD_FPGA_SPI, REG_RUN, 0, buff, read_len);
244 sr_dbg("FPGA register access failed (run state).");
248 run_state = read_u16le_inc(&rdptr);
249 sr_spew("FPGA register: run state 0x%04x.", run_state);
250 if (run_state && (run_state & 0x3) != 0x1) {
251 sr_dbg("Unexpected FPGA register content (run state).");
254 if (run_state && (run_state & ~0xf) != 0x85e0) {
255 sr_dbg("Unexpected FPGA register content (run state).");
259 read_len = sizeof(pwm_en);
260 ret = ctrl_in(sdi, CMD_FPGA_SPI, REG_PWM_EN, 0, buff, read_len);
262 sr_dbg("FPGA register access failed (PWM enable).");
266 pwm_en = read_u8_inc(&rdptr);
267 sr_spew("FPGA register: PWM enable 0x%02x.", pwm_en);
268 if ((pwm_en & 0x3) != 0x0) {
269 sr_dbg("Unexpected FPGA register content (PWM enable).");
273 sr_info("Could re-use current FPGA bitstream. No upload required.");
277 static int upload_fpga_bitstream(const struct sr_dev_inst *sdi,
278 const char *bitstream_fname)
280 struct drv_context *drvc;
281 struct sr_usb_dev_inst *usb;
282 struct sr_resource bitstream;
283 uint32_t bitstream_size;
284 uint8_t buffer[sizeof(uint32_t)];
290 unsigned int zero_pad_to;
292 drvc = sdi->driver->context;
295 sr_info("Uploading FPGA bitstream '%s'.", bitstream_fname);
297 ret = sr_resource_open(drvc->sr_ctx, &bitstream,
298 SR_RESOURCE_FIRMWARE, bitstream_fname);
300 sr_err("Cannot find FPGA bitstream %s.", bitstream_fname);
304 bitstream_size = (uint32_t)bitstream.size;
306 write_u32le_inc(&wrptr, bitstream_size);
307 ret = ctrl_out(sdi, CMD_FPGA_INIT, 0x00, 0, buffer, wrptr - buffer);
309 sr_err("Cannot initiate FPGA bitstream upload.");
310 sr_resource_close(drvc->sr_ctx, &bitstream);
313 zero_pad_to = bitstream_size;
314 zero_pad_to += LA2016_EP2_PADDING - 1;
315 zero_pad_to /= LA2016_EP2_PADDING;
316 zero_pad_to *= LA2016_EP2_PADDING;
320 if (pos < bitstream.size) {
321 len = (int)sr_resource_read(drvc->sr_ctx, &bitstream,
322 block, sizeof(block));
324 sr_err("Cannot read FPGA bitstream.");
325 sr_resource_close(drvc->sr_ctx, &bitstream);
329 /* Zero-pad until 'zero_pad_to'. */
330 len = zero_pad_to - pos;
331 if ((unsigned)len > sizeof(block))
333 memset(&block, 0, len);
338 ret = libusb_bulk_transfer(usb->devhdl, USB_EP_FPGA_BITSTREAM,
339 &block[0], len, &act_len, DEFAULT_TIMEOUT_MS);
341 sr_dbg("Cannot write FPGA bitstream, block %#x len %d: %s.",
342 pos, (int)len, libusb_error_name(ret));
346 if (act_len != len) {
347 sr_dbg("Short write for FPGA bitstream, block %#x len %d: got %d.",
348 pos, (int)len, act_len);
354 sr_resource_close(drvc->sr_ctx, &bitstream);
357 sr_info("FPGA bitstream upload (%" PRIu64 " bytes) done.",
363 static int enable_fpga_bitstream(const struct sr_dev_inst *sdi)
368 ret = ctrl_in(sdi, CMD_FPGA_INIT, 0x00, 0, &resp, sizeof(resp));
370 sr_err("Cannot read response after FPGA bitstream upload.");
374 sr_err("Unexpected FPGA bitstream upload response, got 0x%02x, want 0.",
380 ret = ctrl_out(sdi, CMD_FPGA_ENABLE, 0x01, 0, NULL, 0);
382 sr_err("Cannot enable FPGA after bitstream upload.");
390 static int set_threshold_voltage(const struct sr_dev_inst *sdi, float voltage)
393 uint16_t duty_R79, duty_R56;
394 uint8_t buf[REG_PWM1 - REG_THRESHOLD]; /* Width of REG_THRESHOLD. */
397 /* Clamp threshold setting to valid range for LA2016. */
398 if (voltage > LA2016_THR_VOLTAGE_MAX) {
399 voltage = LA2016_THR_VOLTAGE_MAX;
400 } else if (voltage < -LA2016_THR_VOLTAGE_MAX) {
401 voltage = -LA2016_THR_VOLTAGE_MAX;
405 * Two PWM output channels feed one DAC which generates a bias
406 * voltage, which offsets the input probe's voltage level, and
407 * in combination with the FPGA pins' fixed threshold result in
408 * a programmable input threshold from the user's perspective.
409 * The PWM outputs can be seen on R79 and R56 respectively, the
410 * frequency is 100kHz and the duty cycle varies. The R79 PWM
411 * uses three discrete settings. The R56 PWM varies with desired
412 * thresholds and depends on the R79 PWM configuration. See the
413 * schematics comments which discuss the formulae.
415 if (voltage >= 2.9) {
416 duty_R79 = 0; /* PWM off (0V). */
417 duty_R56 = (uint16_t)(302 * voltage - 363);
418 } else if (voltage > -0.4) {
419 duty_R79 = 0x00f2; /* 25% duty cycle. */
420 duty_R56 = (uint16_t)(302 * voltage + 121);
422 duty_R79 = 0x02d7; /* 72% duty cycle. */
423 duty_R56 = (uint16_t)(302 * voltage + 1090);
426 /* Clamp duty register values to sensible limits. */
429 } else if (duty_R56 > 1100) {
433 sr_dbg("Set threshold voltage %.2fV.", voltage);
434 sr_dbg("Duty cycle values: R56 0x%04x, R79 0x%04x.", duty_R56, duty_R79);
437 write_u16le_inc(&wrptr, duty_R56);
438 write_u16le_inc(&wrptr, duty_R79);
440 ret = ctrl_out(sdi, CMD_FPGA_SPI, REG_THRESHOLD, 0, buf, wrptr - buf);
442 sr_err("Cannot set threshold voltage %.2fV.", voltage);
450 * Communicates a channel's configuration to the device after the
451 * parameters may have changed. Configuration of one channel may
452 * interfere with other channels since they share FPGA registers.
454 static int set_pwm_config(const struct sr_dev_inst *sdi, size_t idx)
456 static uint8_t reg_bases[] = { REG_PWM1, REG_PWM2, };
458 struct dev_context *devc;
459 struct pwm_setting *params;
463 uint32_t period, duty;
466 uint8_t enable_all, enable_cfg, reg_val;
467 uint8_t buf[REG_PWM2 - REG_PWM1]; /* Width of one REG_PWMx. */
471 if (idx >= ARRAY_SIZE(devc->pwm_setting))
473 params = &devc->pwm_setting[idx];
474 if (idx >= ARRAY_SIZE(reg_bases))
476 reg_base = reg_bases[idx];
479 * Map application's specs to hardware register values. Do math
480 * in floating point initially, but convert to u32 eventually.
482 sr_dbg("PWM config, app spec, ch %zu, en %d, freq %.1f, duty %.1f.",
483 idx, params->enabled ? 1 : 0, params->freq, params->duty);
485 val_f /= params->freq;
489 val_f *= params->duty;
494 sr_dbg("PWM config, reg 0x%04x, freq %u, duty %u.",
495 (unsigned)reg_base, (unsigned)period, (unsigned)duty);
497 /* Get the "enabled" state of all supported PWM channels. */
499 for (ch = 0; ch < ARRAY_SIZE(devc->pwm_setting); ch++) {
500 if (!devc->pwm_setting[ch].enabled)
502 enable_all |= 1U << ch;
504 enable_cfg = 1U << idx;
505 sr_spew("PWM config, enable all 0x%02hhx, cfg 0x%02hhx.",
506 enable_all, enable_cfg);
509 * Disable the to-get-configured channel before its parameters
510 * will change. Or disable and exit when the channel is supposed
513 sr_spew("PWM config, disabling before param change.");
514 reg_val = enable_all & ~enable_cfg;
515 ret = ctrl_out(sdi, CMD_FPGA_SPI, REG_PWM_EN, 0,
516 ®_val, sizeof(reg_val));
518 sr_err("Cannot adjust PWM enabled state.");
521 if (!params->enabled)
524 /* Write register values to device. */
525 sr_spew("PWM config, sending new parameters.");
527 write_u32le_inc(&wrptr, period);
528 write_u32le_inc(&wrptr, duty);
529 ret = ctrl_out(sdi, CMD_FPGA_SPI, reg_base, 0, buf, wrptr - buf);
531 sr_err("Cannot change PWM parameters.");
535 /* Enable configured channel after write completion. */
536 sr_spew("PWM config, enabling after param change.");
537 reg_val = enable_all | enable_cfg;
538 ret = ctrl_out(sdi, CMD_FPGA_SPI, REG_PWM_EN, 0,
539 ®_val, sizeof(reg_val));
541 sr_err("Cannot adjust PWM enabled state.");
549 * Determine the number of enabled channels as well as their bitmask
550 * representation. Derive data here which later simplifies processing
551 * of raw capture data memory content in streaming mode.
553 static void la2016_prepare_stream(const struct sr_dev_inst *sdi)
555 struct dev_context *devc;
556 struct stream_state_t *stream;
559 struct sr_channel *ch;
562 stream = &devc->stream;
563 memset(stream, 0, sizeof(*stream));
565 stream->enabled_count = 0;
566 for (l = sdi->channels; l; l = l->next) {
568 if (ch->type != SR_CHANNEL_LOGIC)
572 channel_mask = 1UL << ch->index;
573 stream->enabled_mask |= channel_mask;
574 stream->channel_masks[stream->enabled_count++] = channel_mask;
576 stream->channel_index = 0;
580 * This routine configures the set of enabled channels, as well as the
581 * trigger condition (if one was specified). Also prepares the capture
582 * data processing in stream mode, where the memory layout dramatically
583 * differs from normal mode.
585 static int set_trigger_config(const struct sr_dev_inst *sdi)
587 struct dev_context *devc;
588 struct sr_trigger *trigger;
590 uint32_t channels; /* Actually: Enabled channels? */
591 uint32_t enabled; /* Actually: Triggering channels? */
593 uint32_t high_or_falling;
597 struct sr_trigger_stage *stage1;
598 struct sr_trigger_match *match;
601 uint8_t buf[REG_UNKNOWN_30 - REG_TRIGGER]; /* Width of REG_TRIGGER. */
606 la2016_prepare_stream(sdi);
608 memset(&cfg, 0, sizeof(cfg));
609 cfg.channels = devc->stream.enabled_mask;
611 sr_err("Need at least one enabled logic channel.");
614 trigger = sr_session_trigger_get(sdi->session);
615 if (trigger && trigger->stages) {
616 stages = trigger->stages;
617 stage1 = stages->data;
619 sr_err("Only one trigger stage supported for now.");
622 channel = stage1->matches;
624 match = channel->data;
625 ch_mask = 1UL << match->channel->index;
627 switch (match->match) {
628 case SR_TRIGGER_ZERO:
629 cfg.level |= ch_mask;
630 cfg.high_or_falling &= ~ch_mask;
633 cfg.level |= ch_mask;
634 cfg.high_or_falling |= ch_mask;
636 case SR_TRIGGER_RISING:
637 if ((cfg.enabled & ~cfg.level)) {
638 sr_err("Device only supports one edge trigger.");
641 cfg.level &= ~ch_mask;
642 cfg.high_or_falling &= ~ch_mask;
644 case SR_TRIGGER_FALLING:
645 if ((cfg.enabled & ~cfg.level)) {
646 sr_err("Device only supports one edge trigger.");
649 cfg.level &= ~ch_mask;
650 cfg.high_or_falling |= ch_mask;
653 sr_err("Unknown trigger condition.");
656 cfg.enabled |= ch_mask;
657 channel = channel->next;
660 sr_dbg("Set trigger config: "
661 "enabled-channels 0x%04x, triggering-channels 0x%04x, "
662 "level-triggered 0x%04x, high/falling 0x%04x.",
663 cfg.channels, cfg.enabled, cfg.level, cfg.high_or_falling);
666 * Don't configure hardware trigger parameters in streaming mode
667 * or when the device lacks local memory. Yet the above dump of
668 * derived parameters from user specs is considered valueable.
670 * TODO Add support for soft triggers when hardware triggers in
671 * the device are not used or are not available at all.
673 if (!devc->model->memory_bits || devc->continuous) {
674 if (!devc->model->memory_bits)
675 sr_dbg("Device without memory. No hardware triggers.");
676 else if (devc->continuous)
677 sr_dbg("Streaming mode. No hardware triggers.");
680 cfg.high_or_falling = 0;
683 devc->trigger_involved = cfg.enabled != 0;
686 write_u32le_inc(&wrptr, cfg.channels);
687 write_u32le_inc(&wrptr, cfg.enabled);
688 write_u32le_inc(&wrptr, cfg.level);
689 write_u32le_inc(&wrptr, cfg.high_or_falling);
691 * Comment on this literal 16. Origin, meaning? Cannot be the
692 * register offset, nor the transfer length. Is it a channels
693 * count that is relevant for 16 and 32 channel models? Is it
694 * an obsolete experiment?
696 ret = ctrl_out(sdi, CMD_FPGA_SPI, REG_TRIGGER, 16, buf, wrptr - buf);
698 sr_err("Cannot setup trigger configuration.");
706 * This routine communicates the sample configuration to the device:
707 * Total samples count and samplerate, pre-trigger configuration.
709 static int set_sample_config(const struct sr_dev_inst *sdi)
711 struct dev_context *devc;
712 uint64_t min_samplerate, eff_samplerate;
713 uint64_t stream_bandwidth;
714 uint16_t divider_u16;
715 uint64_t limit_samples;
716 uint64_t pre_trigger_samples;
717 uint64_t pre_trigger_memory;
718 uint8_t buf[REG_TRIGGER - REG_SAMPLING]; /* Width of REG_SAMPLING. */
724 if (devc->samplerate > devc->model->samplerate) {
725 sr_err("Too high a sample rate: %" PRIu64 ".",
729 min_samplerate = devc->model->samplerate;
730 min_samplerate /= 65536;
731 if (devc->samplerate < min_samplerate) {
732 sr_err("Too low a sample rate: %" PRIu64 ".",
736 divider_u16 = devc->model->samplerate / devc->samplerate;
737 eff_samplerate = devc->model->samplerate / divider_u16;
739 ret = sr_sw_limits_get_remain(&devc->sw_limits,
740 &limit_samples, NULL, NULL, NULL);
742 sr_err("Cannot get acquisition limits.");
745 if (limit_samples > LA2016_NUM_SAMPLES_MAX) {
746 sr_warn("Too high a sample depth: %" PRIu64 ", capping.",
748 limit_samples = LA2016_NUM_SAMPLES_MAX;
750 if (limit_samples == 0) {
751 limit_samples = LA2016_NUM_SAMPLES_MAX;
752 sr_dbg("Passing %" PRIu64 " to HW for unlimited samples.",
757 * The acquisition configuration communicates "pre-trigger"
758 * specs in several formats. sigrok users provide a percentage
759 * (0-100%), which translates to a pre-trigger samples count
760 * (assuming that a total samples count limit was specified).
761 * The device supports hardware compression, which depends on
762 * slowly changing input data to be effective. Fast changing
763 * input data may occupy more space in sample memory than its
764 * uncompressed form would. This is why a third parameter can
765 * limit the amount of sample memory to use for pre-trigger
766 * data. Only the upper 24 bits of that memory size spec get
767 * communicated to the device (written to its FPGA register).
769 if (!devc->model->memory_bits) {
770 sr_dbg("Memory-less device, skipping pre-trigger config.");
771 pre_trigger_samples = 0;
772 pre_trigger_memory = 0;
773 } else if (devc->trigger_involved) {
774 pre_trigger_samples = limit_samples;
775 pre_trigger_samples *= devc->capture_ratio;
776 pre_trigger_samples /= 100;
777 pre_trigger_memory = devc->model->memory_bits;
778 pre_trigger_memory *= UINT64_C(1024 * 1024 * 1024);
779 pre_trigger_memory /= 8; /* devc->model->channel_count ? */
780 pre_trigger_memory *= devc->capture_ratio;
781 pre_trigger_memory /= 100;
783 sr_dbg("No trigger setup, skipping pre-trigger config.");
784 pre_trigger_samples = 0;
785 pre_trigger_memory = 0;
787 /* Ensure non-zero value after LSB shift out in HW reg. */
788 if (pre_trigger_memory < 0x100)
789 pre_trigger_memory = 0x100;
791 sr_dbg("Set sample config: %" PRIu64 "kHz (div %" PRIu16 "), %" PRIu64 " samples.",
792 eff_samplerate / SR_KHZ(1), divider_u16, limit_samples);
793 sr_dbg("Capture ratio %" PRIu64 "%%, count %" PRIu64 ", mem %" PRIu64 ".",
794 devc->capture_ratio, pre_trigger_samples, pre_trigger_memory);
796 if (devc->continuous) {
797 stream_bandwidth = eff_samplerate;
798 stream_bandwidth *= devc->stream.enabled_count;
799 sr_dbg("Streaming: channel count %zu, product %" PRIu64 ".",
800 devc->stream.enabled_count, stream_bandwidth);
801 stream_bandwidth /= 1000 * 1000;
802 if (stream_bandwidth >= LA2016_STREAM_MBPS_MAX) {
803 sr_warn("High USB stream bandwidth: %" PRIu64 "Mbps.",
806 if (stream_bandwidth < LA2016_STREAM_PUSH_THR) {
807 sr_dbg("Streaming: low Mbps, suggest periodic flush.");
808 devc->stream.flush_period_ms = LA2016_STREAM_PUSH_IVAL;
813 * The acquisition configuration occupies a total of 16 bytes:
814 * - A 34bit total samples count limit (up to 10 billions) that
815 * is kept in a 40bit register.
816 * - A 34bit pre-trigger samples count limit (up to 10 billions)
817 * in another 40bit register.
818 * - A 32bit pre-trigger memory space limit (in bytes) of which
819 * the upper 24bits are kept in an FPGA register.
820 * - A 16bit clock divider which gets applied to the maximum
821 * samplerate of the device.
822 * - An 8bit register of unknown meaning. Currently always 0.
825 write_u40le_inc(&wrptr, limit_samples);
826 write_u40le_inc(&wrptr, pre_trigger_samples);
827 write_u24le_inc(&wrptr, pre_trigger_memory >> 8);
828 write_u16le_inc(&wrptr, divider_u16);
829 write_u8_inc(&wrptr, 0);
830 ret = ctrl_out(sdi, CMD_FPGA_SPI, REG_SAMPLING, 0, buf, wrptr - buf);
832 sr_err("Cannot setup acquisition configuration.");
840 * FPGA register REG_RUN holds the run state (u16le format). Bit fields
842 * bit 0: value 1 = idle
843 * bit 1: value 1 = writing to SDRAM
844 * bit 2: value 0 = waiting for trigger, 1 = trigger seen
845 * bit 3: value 0 = pretrigger sampling, 1 = posttrigger sampling
846 * The meaning of other bit fields is unknown.
848 * Typical values in order of appearance during execution:
849 * 0x85e1: idle, no acquisition pending
850 * IDLE set, TRGD don't care, POST don't care; DRAM don't care
851 * "In idle state." Takes precedence over all others.
852 * 0x85e2: pre-sampling, samples before the trigger position,
853 * when capture ratio > 0%
854 * IDLE clear, TRGD clear, POST clear; DRAM don't care
855 * "Not idle any more, no post yet, not triggered yet."
856 * 0x85ea: pre-sampling complete, now waiting for the trigger
857 * (whilst sampling continuously)
858 * IDLE clear, TRGD clear, POST set; DRAM don't care
859 * "Post set thus after pre, not triggered yet"
860 * 0x85ee: trigger seen, capturing post-trigger samples, running
861 * IDLE clear, TRGD set, POST set; DRAM don't care
862 * "Triggered and in post, not idle yet."
864 * IDLE set, TRGD don't care, POST don't care; DRAM don't care
865 * "In idle state." TRGD/POST don't care, same meaning as above.
867 static const uint16_t runstate_mask_idle = RUNSTATE_IDLE_BIT;
868 static const uint16_t runstate_patt_idle = RUNSTATE_IDLE_BIT;
869 static const uint16_t runstate_mask_step =
870 RUNSTATE_IDLE_BIT | RUNSTATE_TRGD_BIT | RUNSTATE_POST_BIT;
871 static const uint16_t runstate_patt_pre_trig = 0;
872 static const uint16_t runstate_patt_wait_trig = RUNSTATE_POST_BIT;
873 static const uint16_t runstate_patt_post_trig =
874 RUNSTATE_TRGD_BIT | RUNSTATE_POST_BIT;
876 static uint16_t run_state(const struct sr_dev_inst *sdi)
878 static uint16_t previous_state;
882 uint8_t buff[REG_PWM_EN - REG_RUN]; /* Width of REG_RUN. */
883 const uint8_t *rdptr;
886 ret = ctrl_in(sdi, CMD_FPGA_SPI, REG_RUN, 0, buff, sizeof(state));
888 sr_err("Cannot read run state.");
892 state = read_u16le_inc(&rdptr);
895 * Avoid flooding the log, only dump values as they change.
896 * The routine is called about every 50ms.
898 if (state == previous_state)
901 previous_state = state;
903 if ((state & runstate_mask_idle) == runstate_patt_idle)
905 if ((state & runstate_mask_step) == runstate_patt_pre_trig)
906 label = "pre-trigger sampling";
907 if ((state & runstate_mask_step) == runstate_patt_wait_trig)
908 label = "sampling, waiting for trigger";
909 if ((state & runstate_mask_step) == runstate_patt_post_trig)
910 label = "post-trigger sampling";
912 sr_dbg("Run state: 0x%04x (%s).", state, label);
914 sr_dbg("Run state: 0x%04x.", state);
919 static gboolean la2016_is_idle(const struct sr_dev_inst *sdi)
923 state = run_state(sdi);
924 if ((state & runstate_mask_idle) == runstate_patt_idle)
930 static int set_run_mode(const struct sr_dev_inst *sdi, uint8_t mode)
934 ret = ctrl_out(sdi, CMD_FPGA_SPI, REG_RUN, 0, &mode, sizeof(mode));
936 sr_err("Cannot configure run mode %d.", mode);
943 static int get_capture_info(const struct sr_dev_inst *sdi)
945 struct dev_context *devc;
947 uint8_t buf[REG_TRIGGER - REG_SAMPLING]; /* Width of REG_SAMPLING. */
948 const uint8_t *rdptr;
952 ret = ctrl_in(sdi, CMD_FPGA_SPI, REG_SAMPLING, 0, buf, sizeof(buf));
954 sr_err("Cannot read capture info.");
959 devc->info.n_rep_packets = read_u32le_inc(&rdptr);
960 devc->info.n_rep_packets_before_trigger = read_u32le_inc(&rdptr);
961 devc->info.write_pos = read_u32le_inc(&rdptr);
963 sr_dbg("Capture info: n_rep_packets: 0x%08x/%d, before_trigger: 0x%08x/%d, write_pos: 0x%08x/%d.",
964 devc->info.n_rep_packets, devc->info.n_rep_packets,
965 devc->info.n_rep_packets_before_trigger,
966 devc->info.n_rep_packets_before_trigger,
967 devc->info.write_pos, devc->info.write_pos);
969 if (devc->info.n_rep_packets % devc->packets_per_chunk) {
970 sr_warn("Unexpected packets count %lu, not a multiple of %lu.",
971 (unsigned long)devc->info.n_rep_packets,
972 (unsigned long)devc->packets_per_chunk);
978 SR_PRIV int la2016_upload_firmware(const struct sr_dev_inst *sdi,
979 struct sr_context *sr_ctx, libusb_device *dev, gboolean skip_upload)
981 struct dev_context *devc;
986 devc = sdi ? sdi->priv : NULL;
987 if (!devc || !devc->usb_pid)
991 fw = g_strdup_printf(MCU_FWFILE_FMT, pid);
992 sr_info("USB PID %04hx, MCU firmware '%s'.", pid, fw);
993 devc->mcu_firmware = g_strdup(fw);
998 ret = ezusb_upload_firmware(sr_ctx, dev, USB_CONFIGURATION, fw);
1006 static void LIBUSB_CALL receive_transfer(struct libusb_transfer *xfer);
1008 static void la2016_usbxfer_release_cb(gpointer p)
1010 struct libusb_transfer *xfer;
1013 g_free(xfer->buffer);
1014 libusb_free_transfer(xfer);
1017 static int la2016_usbxfer_release(const struct sr_dev_inst *sdi)
1019 struct dev_context *devc;
1021 devc = sdi ? sdi->priv : NULL;
1025 /* Release all USB transfers. */
1026 g_slist_free_full(devc->transfers, la2016_usbxfer_release_cb);
1027 devc->transfers = NULL;
1032 static int la2016_usbxfer_allocate(const struct sr_dev_inst *sdi)
1034 struct dev_context *devc;
1035 size_t bufsize, xfercount;
1037 struct libusb_transfer *xfer;
1039 devc = sdi ? sdi->priv : NULL;
1043 /* Transfers were already allocated before? */
1044 if (devc->transfers)
1048 * Allocate all USB transfers and their buffers. Arrange for a
1049 * buffer size which is within the device's capabilities, and
1050 * is a multiple of the USB endpoint's size, to make use of the
1051 * RAW_IO performance feature.
1053 * Implementation detail: The LA2016_USB_BUFSZ value happens
1054 * to match all those constraints. No additional arithmetics is
1055 * required in this location.
1057 bufsize = LA2016_USB_BUFSZ;
1058 xfercount = LA2016_USB_XFER_COUNT;
1059 while (xfercount--) {
1060 buffer = g_try_malloc(bufsize);
1062 sr_err("Cannot allocate USB transfer buffer.");
1063 return SR_ERR_MALLOC;
1065 xfer = libusb_alloc_transfer(0);
1067 sr_err("Cannot allocate USB transfer.");
1069 return SR_ERR_MALLOC;
1071 xfer->buffer = buffer;
1072 devc->transfers = g_slist_append(devc->transfers, xfer);
1074 devc->transfer_bufsize = bufsize;
1079 static int la2016_usbxfer_cancel_all(const struct sr_dev_inst *sdi)
1081 struct dev_context *devc;
1083 struct libusb_transfer *xfer;
1085 devc = sdi ? sdi->priv : NULL;
1089 /* Unconditionally cancel the transfer. Ignore errors. */
1090 for (l = devc->transfers; l; l = l->next) {
1094 libusb_cancel_transfer(xfer);
1100 static int la2016_usbxfer_resubmit(const struct sr_dev_inst *sdi,
1101 struct libusb_transfer *xfer)
1103 struct dev_context *devc;
1104 struct sr_usb_dev_inst *usb;
1105 libusb_transfer_cb_fn cb;
1108 devc = sdi ? sdi->priv : NULL;
1109 usb = sdi ? sdi->conn : NULL;
1116 cb = receive_transfer;
1117 libusb_fill_bulk_transfer(xfer, usb->devhdl,
1118 USB_EP_CAPTURE_DATA | LIBUSB_ENDPOINT_IN,
1119 xfer->buffer, devc->transfer_bufsize,
1120 cb, (void *)sdi, CAPTURE_TIMEOUT_MS);
1121 ret = libusb_submit_transfer(xfer);
1123 sr_err("Cannot submit USB transfer: %s.",
1124 libusb_error_name(ret));
1131 static int la2016_usbxfer_submit_all(const struct sr_dev_inst *sdi)
1133 struct dev_context *devc;
1135 struct libusb_transfer *xfer;
1138 devc = sdi ? sdi->priv : NULL;
1142 for (l = devc->transfers; l; l = l->next) {
1146 ret = la2016_usbxfer_resubmit(sdi, xfer);
1154 SR_PRIV int la2016_setup_acquisition(const struct sr_dev_inst *sdi,
1157 struct dev_context *devc;
1163 ret = set_threshold_voltage(sdi, voltage);
1167 cmd = devc->continuous ? CAPTMODE_STREAM : CAPTMODE_TO_RAM;
1168 ret = ctrl_out(sdi, CMD_FPGA_SPI, REG_CAPT_MODE, 0, &cmd, sizeof(cmd));
1170 sr_err("Cannot send command to stop sampling.");
1174 ret = set_trigger_config(sdi);
1178 ret = set_sample_config(sdi);
1185 SR_PRIV int la2016_start_acquisition(const struct sr_dev_inst *sdi)
1187 struct dev_context *devc;
1192 ret = la2016_usbxfer_allocate(sdi);
1196 if (devc->continuous) {
1197 ret = ctrl_out(sdi, CMD_BULK_RESET, 0x00, 0, NULL, 0);
1201 ret = la2016_usbxfer_submit_all(sdi);
1206 * Periodic receive callback will set runmode. This
1207 * activity MUST be close to data reception, a pause
1208 * between these steps breaks the stream's operation.
1211 ret = set_run_mode(sdi, RUNMODE_RUN);
1219 static int la2016_stop_acquisition(const struct sr_dev_inst *sdi)
1221 struct dev_context *devc;
1224 ret = set_run_mode(sdi, RUNMODE_HALT);
1229 if (devc->continuous)
1230 devc->download_finished = TRUE;
1235 SR_PRIV int la2016_abort_acquisition(const struct sr_dev_inst *sdi)
1239 ret = la2016_stop_acquisition(sdi);
1243 (void)la2016_usbxfer_cancel_all(sdi);
1248 static int la2016_start_download(const struct sr_dev_inst *sdi)
1250 struct dev_context *devc;
1252 uint8_t wrbuf[REG_SAMPLING - REG_BULK]; /* Width of REG_BULK. */
1257 ret = get_capture_info(sdi);
1261 devc->n_transfer_packets_to_read = devc->info.n_rep_packets;
1262 devc->n_transfer_packets_to_read /= devc->packets_per_chunk;
1263 devc->n_bytes_to_read = devc->n_transfer_packets_to_read;
1264 devc->n_bytes_to_read *= TRANSFER_PACKET_LENGTH;
1265 devc->read_pos = devc->info.write_pos - devc->n_bytes_to_read;
1266 devc->n_reps_until_trigger = devc->info.n_rep_packets_before_trigger;
1268 sr_dbg("Want to read %u xfer-packets starting from pos %" PRIu32 ".",
1269 devc->n_transfer_packets_to_read, devc->read_pos);
1271 ret = ctrl_out(sdi, CMD_BULK_RESET, 0x00, 0, NULL, 0);
1273 sr_err("Cannot reset USB bulk state.");
1276 sr_dbg("Will read from 0x%08lx, 0x%08x bytes.",
1277 (unsigned long)devc->read_pos, devc->n_bytes_to_read);
1279 write_u32le_inc(&wrptr, devc->read_pos);
1280 write_u32le_inc(&wrptr, devc->n_bytes_to_read);
1281 ret = ctrl_out(sdi, CMD_FPGA_SPI, REG_BULK, 0, wrbuf, wrptr - wrbuf);
1283 sr_err("Cannot send USB bulk config.");
1287 ret = la2016_usbxfer_submit_all(sdi);
1289 sr_err("Cannot submit USB bulk transfers.");
1293 ret = ctrl_out(sdi, CMD_BULK_START, 0x00, 0, NULL, 0);
1295 sr_err("Cannot start USB bulk transfers.");
1303 * A chunk (received via USB) contains a number of transfers (USB length
1304 * divided by 16) which contain a number of packets (5 per transfer) which
1305 * contain a number of samples (8bit repeat count per 16bit sample data).
1307 static void send_chunk(struct sr_dev_inst *sdi,
1308 const uint8_t *data_buffer, size_t data_length)
1310 struct dev_context *devc;
1311 size_t num_xfers, num_pkts;
1313 uint32_t sample_value;
1315 uint8_t sample_buff[sizeof(sample_value)];
1319 /* Ignore incoming USB data after complete sample data download. */
1320 if (devc->download_finished)
1323 if (devc->trigger_involved && !devc->trigger_marked && devc->info.n_rep_packets_before_trigger == 0) {
1324 feed_queue_logic_send_trigger(devc->feed_queue);
1325 devc->trigger_marked = TRUE;
1329 * Adjust the number of remaining bytes to read from the device
1330 * before the processing of the currently received chunk affects
1331 * the variable which holds the number of received bytes.
1333 if (data_length > devc->n_bytes_to_read)
1334 devc->n_bytes_to_read = 0;
1336 devc->n_bytes_to_read -= data_length;
1338 /* Process the received chunk of capture data. */
1341 num_xfers = data_length / TRANSFER_PACKET_LENGTH;
1342 while (num_xfers--) {
1343 num_pkts = devc->packets_per_chunk;
1344 while (num_pkts--) {
1346 /* TODO Verify 32channel layout. */
1347 if (devc->model->channel_count == 32)
1348 sample_value = read_u32le_inc(&rp);
1349 else if (devc->model->channel_count == 16)
1350 sample_value = read_u16le_inc(&rp);
1351 repetitions = read_u8_inc(&rp);
1353 devc->total_samples += repetitions;
1355 write_u32le(sample_buff, sample_value);
1356 feed_queue_logic_submit(devc->feed_queue,
1357 sample_buff, repetitions);
1358 sr_sw_limits_update_samples_read(&devc->sw_limits,
1361 if (devc->trigger_involved && !devc->trigger_marked) {
1362 if (!--devc->n_reps_until_trigger) {
1363 feed_queue_logic_send_trigger(devc->feed_queue);
1364 devc->trigger_marked = TRUE;
1365 sr_dbg("Trigger position after %" PRIu64 " samples, %.6fms.",
1366 devc->total_samples,
1367 (double)devc->total_samples / devc->samplerate * 1e3);
1371 (void)read_u8_inc(&rp); /* Skip sequence number. */
1375 * Check for several conditions which shall terminate the
1376 * capture data download: When the amount of capture data in
1377 * the device is exhausted. When the user specified samples
1378 * count limit is reached.
1380 if (!devc->n_bytes_to_read) {
1381 devc->download_finished = TRUE;
1383 sr_dbg("%" PRIu32 " more bytes to download from the device.",
1384 devc->n_bytes_to_read);
1386 if (!devc->download_finished && sr_sw_limits_check(&devc->sw_limits)) {
1387 sr_dbg("Acquisition limit reached.");
1388 devc->download_finished = TRUE;
1390 if (devc->download_finished) {
1391 sr_dbg("Download finished, flushing session feed queue.");
1392 feed_queue_logic_flush(devc->feed_queue);
1394 sr_dbg("Total samples after chunk: %" PRIu64 ".", devc->total_samples);
1398 * Process a chunk of capture data in streaming mode. The memory layout
1399 * is rather different from "normal mode" (see the send_chunk() routine
1400 * above). In streaming mode data is not compressed, and memory cells
1401 * neither contain raw sampled pin values at a given point in time. The
1402 * memory content needs transformation.
1403 * - The memory content can be seen as a sequence of memory cells.
1404 * - Each cell contains samples that correspond to the same channel.
1405 * The next cell contains samples for the next channel, etc.
1406 * - Only enabled channels occupy memory cells. Disabled channels are
1407 * not part of the capture data memory layout.
1408 * - The LSB bit position in a cell is the sample which was taken first
1409 * for this channel. Upper bit positions were taken later.
1411 * Implementor's note: This routine is inspired by convert_sample_data()
1412 * in the https://github.com/AlexUg/sigrok implementation. Which in turn
1413 * appears to have been derived from the saleae-logic16 sigrok driver.
1414 * The code is phrased conservatively to verify the layout as discussed
1415 * above, performance was not a priority. Operation was verified with an
1416 * LA2016 device. The memory layout of 32 channel models is yet to get
1419 static void stream_data(struct sr_dev_inst *sdi,
1420 const uint8_t *data_buffer, size_t data_length)
1422 struct dev_context *devc;
1423 struct stream_state_t *stream;
1426 uint32_t sample_value;
1427 uint8_t sample_buff[sizeof(sample_value)];
1432 stream = &devc->stream;
1434 /* Ignore incoming USB data after complete sample data download. */
1435 if (devc->download_finished)
1437 sr_dbg("Stream mode, got another chunk: %p, length %zu.",
1438 data_buffer, data_length);
1440 /* TODO Add soft trigger support when in stream mode? */
1443 * TODO Are memory cells always as wide as the channel count?
1444 * Are they always 16bits wide? Verify for 32 channel devices.
1446 bit_count = devc->model->channel_count;
1447 if (bit_count == 32) {
1448 data_length /= sizeof(uint32_t);
1449 } else if (bit_count == 16) {
1450 data_length /= sizeof(uint16_t);
1453 * Unhandled case. Acquisition should not start.
1454 * The statement silences the compiler.
1460 while (data_length--) {
1461 /* Get another entity. */
1462 if (bit_count == 32)
1463 sample_value = read_u32le_inc(&rp);
1464 else if (bit_count == 16)
1465 sample_value = read_u16le_inc(&rp);
1467 /* Map the entity's bits to a channel's samples. */
1468 ch_mask = stream->channel_masks[stream->channel_index];
1469 for (bit_idx = 0; bit_idx < bit_count; bit_idx++) {
1470 if (sample_value & (1UL << bit_idx))
1471 stream->sample_data[bit_idx] |= ch_mask;
1475 * Advance to the next channel. Submit a block of
1476 * samples when all channels' data was seen.
1478 stream->channel_index++;
1479 if (stream->channel_index != stream->enabled_count)
1481 for (bit_idx = 0; bit_idx < bit_count; bit_idx++) {
1482 sample_value = stream->sample_data[bit_idx];
1483 write_u32le(sample_buff, sample_value);
1484 feed_queue_logic_submit(devc->feed_queue, sample_buff, 1);
1486 sr_sw_limits_update_samples_read(&devc->sw_limits, bit_count);
1487 devc->total_samples += bit_count;
1488 memset(stream->sample_data, 0, sizeof(stream->sample_data));
1489 stream->channel_index = 0;
1493 * Need we count empty or failed USB transfers? This version
1494 * doesn't, assumes that timeouts are perfectly legal because
1495 * transfers are started early, and slow samplerates or trigger
1496 * support in hardware are plausible causes for empty transfers.
1498 * TODO Maybe a good condition would be (rather large) a timeout
1499 * after a previous capture data chunk was seen? So that stalled
1500 * streaming gets detected which _is_ an exceptional condition.
1501 * We have observed these when "runmode" is set early but bulk
1502 * transfers start late with a pause after setting the runmode.
1504 if (sr_sw_limits_check(&devc->sw_limits)) {
1505 sr_dbg("Acquisition end reached (sw limits).");
1506 devc->download_finished = TRUE;
1508 if (devc->download_finished) {
1509 sr_dbg("Stream receive done, flushing session feed queue.");
1510 feed_queue_logic_flush(devc->feed_queue);
1512 sr_dbg("Total samples after chunk: %" PRIu64 ".", devc->total_samples);
1515 static void LIBUSB_CALL receive_transfer(struct libusb_transfer *transfer)
1517 struct sr_dev_inst *sdi;
1518 struct dev_context *devc;
1519 gboolean was_cancelled, device_gone;
1522 sdi = transfer->user_data;
1525 was_cancelled = transfer->status == LIBUSB_TRANSFER_CANCELLED;
1526 device_gone = transfer->status == LIBUSB_TRANSFER_NO_DEVICE;
1527 sr_dbg("receive_transfer(): status %s received %d bytes.",
1528 libusb_error_name(transfer->status), transfer->actual_length);
1530 sr_warn("Lost communication to USB device.");
1531 devc->download_finished = TRUE;
1536 * Implementation detail: A USB transfer timeout is not fatal
1537 * here. We just process whatever was received, empty input is
1538 * perfectly acceptable. Reaching (or exceeding) the sw limits
1539 * or exhausting the device's captured data will complete the
1540 * sample data download.
1542 if (devc->continuous)
1543 stream_data(sdi, transfer->buffer, transfer->actual_length);
1545 send_chunk(sdi, transfer->buffer, transfer->actual_length);
1548 * Re-submit completed transfers (regardless of timeout or
1549 * data reception), unless the transfer was cancelled when
1550 * the acquisition was terminated or has completed.
1552 if (!was_cancelled && !devc->download_finished) {
1553 ret = la2016_usbxfer_resubmit(sdi, transfer);
1556 devc->download_finished = TRUE;
1560 SR_PRIV int la2016_receive_data(int fd, int revents, void *cb_data)
1562 const struct sr_dev_inst *sdi;
1563 struct dev_context *devc;
1564 struct drv_context *drvc;
1573 drvc = sdi->driver->context;
1575 /* Arrange for the start of stream mode when requested. */
1576 if (devc->continuous && !devc->frame_begin_sent) {
1577 sr_dbg("First receive callback in stream mode.");
1578 devc->download_finished = FALSE;
1579 devc->trigger_marked = FALSE;
1580 devc->total_samples = 0;
1582 std_session_send_df_frame_begin(sdi);
1583 devc->frame_begin_sent = TRUE;
1585 ret = set_run_mode(sdi, RUNMODE_RUN);
1587 sr_err("Cannot set 'runmode' to 'run'.");
1591 ret = ctrl_out(sdi, CMD_BULK_START, 0x00, 0, NULL, 0);
1593 sr_err("Cannot start USB bulk transfers.");
1596 sr_dbg("Stream data reception initiated.");
1600 * Wait for the acquisition to complete in hardware.
1601 * Periodically check a potentially configured msecs timeout.
1603 if (!devc->continuous && !devc->completion_seen) {
1604 if (!la2016_is_idle(sdi)) {
1605 if (sr_sw_limits_check(&devc->sw_limits)) {
1606 devc->sw_limits.limit_msec = 0;
1607 sr_dbg("Limit reached. Stopping acquisition.");
1608 la2016_stop_acquisition(sdi);
1610 /* Not yet ready for sample data download. */
1613 sr_dbg("Acquisition completion seen (hardware).");
1614 devc->sw_limits.limit_msec = 0;
1615 devc->completion_seen = TRUE;
1616 devc->download_finished = FALSE;
1617 devc->trigger_marked = FALSE;
1618 devc->total_samples = 0;
1620 la2016_dump_fpga_registers(sdi, "acquisition complete", 0, 0);
1622 /* Initiate the download of acquired sample data. */
1623 std_session_send_df_frame_begin(sdi);
1624 devc->frame_begin_sent = TRUE;
1625 ret = la2016_start_download(sdi);
1627 sr_err("Cannot start acquisition data download.");
1630 sr_dbg("Acquisition data download started.");
1635 /* Handle USB reception. Drives sample data download. */
1636 memset(&tv, 0, sizeof(tv));
1637 libusb_handle_events_timeout(drvc->sr_ctx->libusb_ctx, &tv);
1640 * Periodically flush acquisition data in streaming mode.
1641 * Without this nudge, previously received and accumulated data
1642 * keeps sitting in queues and is not seen by applications.
1644 if (devc->continuous && devc->stream.flush_period_ms) {
1645 uint64_t now, elapsed;
1646 now = g_get_monotonic_time();
1647 if (!devc->stream.last_flushed)
1648 devc->stream.last_flushed = now;
1649 elapsed = now - devc->stream.last_flushed;
1651 if (elapsed >= devc->stream.flush_period_ms) {
1652 sr_dbg("Stream mode, flushing.");
1653 feed_queue_logic_flush(devc->feed_queue);
1654 devc->stream.last_flushed = now;
1658 /* Postprocess completion of sample data download. */
1659 if (devc->download_finished) {
1660 sr_dbg("Download finished, post processing.");
1662 la2016_stop_acquisition(sdi);
1663 usb_source_remove(sdi->session, drvc->sr_ctx);
1665 la2016_usbxfer_cancel_all(sdi);
1666 memset(&tv, 0, sizeof(tv));
1667 libusb_handle_events_timeout(drvc->sr_ctx->libusb_ctx, &tv);
1669 feed_queue_logic_flush(devc->feed_queue);
1670 feed_queue_logic_free(devc->feed_queue);
1671 devc->feed_queue = NULL;
1672 if (devc->frame_begin_sent) {
1673 std_session_send_df_frame_end(sdi);
1674 devc->frame_begin_sent = FALSE;
1676 std_session_send_df_end(sdi);
1678 sr_dbg("Download finished, done post processing.");
1684 SR_PRIV int la2016_identify_device(const struct sr_dev_inst *sdi,
1685 gboolean show_message)
1687 struct dev_context *devc;
1688 uint8_t buf[8]; /* Larger size of manuf date and device type magic. */
1689 size_t rdoff, rdlen;
1690 const uint8_t *rdptr;
1691 uint8_t date_yy, date_mm;
1692 uint8_t dinv_yy, dinv_mm;
1695 const struct kingst_model *model;
1701 * Four EEPROM bytes at offset 0x20 are the manufacturing date,
1702 * year and month in BCD format, followed by inverted values for
1703 * consistency checks. For example bytes 20 04 df fb translate
1704 * to 2020-04. This information can help identify the vintage of
1705 * devices when unknown magic numbers are seen.
1708 rdlen = 4 * sizeof(uint8_t);
1709 ret = ctrl_in(sdi, CMD_EEPROM, rdoff, 0, buf, rdlen);
1710 if (ret != SR_OK && !show_message) {
1711 /* Non-fatal weak attempt during probe. Not worth logging. */
1712 sr_dbg("Cannot access EEPROM.");
1714 } else if (ret != SR_OK) {
1715 /* Failed attempt in regular use. Non-fatal. Worth logging. */
1716 sr_err("Cannot read manufacture date in EEPROM.");
1718 if (sr_log_loglevel_get() >= SR_LOG_SPEW) {
1720 txt = sr_hexdump_new(buf, rdlen);
1721 sr_spew("Manufacture date bytes %s.", txt->str);
1722 sr_hexdump_free(txt);
1725 date_yy = read_u8_inc(&rdptr);
1726 date_mm = read_u8_inc(&rdptr);
1727 dinv_yy = read_u8_inc(&rdptr);
1728 dinv_mm = read_u8_inc(&rdptr);
1729 sr_info("Manufacture date: 20%02hx-%02hx.", date_yy, date_mm);
1730 if ((date_mm ^ dinv_mm) != 0xff || (date_yy ^ dinv_yy) != 0xff)
1731 sr_warn("Manufacture date fails checksum test.");
1735 * Several Kingst logic analyzer devices share the same USB VID
1736 * and PID. The product ID determines which MCU firmware to load.
1737 * The MCU firmware provides access to EEPROM content which then
1738 * allows to identify the device model. Which in turn determines
1739 * which FPGA bitstream to load. Eight bytes at offset 0x08 are
1742 * EEPROM content for model identification is kept redundantly
1743 * in memory. The values are stored in verbatim and in inverted
1744 * form, multiple copies are kept at different offsets. Example
1755 * Exclusively inspecting the magic byte appears to be sufficient,
1756 * other fields seem to be 'don't care'.
1758 * magic 2 == LA2016 using "kingst-la2016-fpga.bitstream"
1759 * magic 3 == LA1016 using "kingst-la1016-fpga.bitstream"
1760 * magic 8 == LA2016a using "kingst-la2016a1-fpga.bitstream"
1761 * (latest v1.3.0 PCB, perhaps others)
1762 * magic 9 == LA1016a using "kingst-la1016a1-fpga.bitstream"
1763 * (latest v1.3.0 PCB, perhaps others)
1765 * When EEPROM content does not match the hardware configuration
1766 * (the board layout), the software may load but yield incorrect
1767 * results (like swapped channels). The FPGA bitstream itself
1768 * will authenticate with IC U10 and fail when its capabilities
1769 * do not match the hardware model. An LA1016 won't become a
1770 * LA2016 by faking its EEPROM content.
1772 devc->identify_magic = 0;
1774 rdlen = 8 * sizeof(uint8_t);
1775 ret = ctrl_in(sdi, CMD_EEPROM, rdoff, 0, &buf, rdlen);
1777 sr_err("Cannot read EEPROM device identifier bytes.");
1780 if (sr_log_loglevel_get() >= SR_LOG_SPEW) {
1782 txt = sr_hexdump_new(buf, rdlen);
1783 sr_spew("EEPROM magic bytes %s.", txt->str);
1784 sr_hexdump_free(txt);
1786 if ((buf[0] ^ buf[1]) == 0xff) {
1787 /* Primary copy of magic passes complement check. */
1789 sr_dbg("Using primary magic, value %d.", (int)magic);
1790 } else if ((buf[4] ^ buf[5]) == 0xff) {
1791 /* Backup copy of magic passes complement check. */
1793 sr_dbg("Using backup magic, value %d.", (int)magic);
1795 sr_err("Cannot find consistent device type identification.");
1798 devc->identify_magic = magic;
1801 for (model_idx = 0; model_idx < ARRAY_SIZE(models); model_idx++) {
1802 model = &models[model_idx];
1803 if (model->magic != magic)
1805 devc->model = model;
1806 sr_info("Model '%s', %zu channels, max %" PRIu64 "MHz.",
1807 model->name, model->channel_count,
1808 model->samplerate / SR_MHZ(1));
1809 devc->fpga_bitstream = g_strdup_printf(FPGA_FWFILE_FMT,
1811 sr_info("FPGA bitstream file '%s'.", devc->fpga_bitstream);
1815 sr_err("Cannot identify as one of the supported models.");
1822 SR_PRIV int la2016_init_hardware(const struct sr_dev_inst *sdi)
1824 struct dev_context *devc;
1825 const char *bitstream_fn;
1830 bitstream_fn = devc ? devc->fpga_bitstream : "";
1832 ret = check_fpga_bitstream(sdi);
1834 ret = upload_fpga_bitstream(sdi, bitstream_fn);
1836 sr_err("Cannot upload FPGA bitstream.");
1840 ret = enable_fpga_bitstream(sdi);
1842 sr_err("Cannot enable FPGA bitstream after upload.");
1846 state = run_state(sdi);
1847 if ((state & 0xfff0) != 0x85e0) {
1848 sr_warn("Unexpected run state, want 0x85eX, got 0x%04x.", state);
1851 ret = ctrl_out(sdi, CMD_BULK_RESET, 0x00, 0, NULL, 0);
1853 sr_err("Cannot reset USB bulk transfer.");
1857 sr_dbg("Device should be initialized.");
1862 SR_PRIV int la2016_deinit_hardware(const struct sr_dev_inst *sdi)
1866 ret = ctrl_out(sdi, CMD_FPGA_ENABLE, 0x00, 0, NULL, 0);
1868 sr_err("Cannot deinitialize device's FPGA.");
1875 SR_PRIV void la2016_release_resources(const struct sr_dev_inst *sdi)
1877 (void)la2016_usbxfer_release(sdi);
1880 SR_PRIV int la2016_write_pwm_config(const struct sr_dev_inst *sdi, size_t idx)
1882 return set_pwm_config(sdi, idx);