2 * This file is part of the libsigrok project.
4 * Copyright (C) 2020 Florian Schmidt <schmidt_florian@gmx.de>
5 * Copyright (C) 2013 Marcus Comstedt <marcus@mc.pp.se>
6 * Copyright (C) 2013 Bert Vermeulen <bert@biot.com>
7 * Copyright (C) 2012 Joel Holdsworth <joel@airwebreathe.org.uk>
9 * This program is free software: you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation, either version 3 of the License, or
12 * (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program. If not, see <http://www.gnu.org/licenses/>.
27 #include <glib/gstdio.h>
29 #include <libsigrok/libsigrok.h>
35 #include "libsigrok-internal.h"
38 #define UC_FIRMWARE "kingst-la-%04x.fw"
39 #define FPGA_FW_LA2016 "kingst-la2016-fpga.bitstream"
40 #define FPGA_FW_LA2016A "kingst-la2016a1-fpga.bitstream"
41 #define FPGA_FW_LA1016 "kingst-la1016-fpga.bitstream"
42 #define FPGA_FW_LA1016A "kingst-la1016a1-fpga.bitstream"
44 #define MAX_SAMPLE_RATE_LA2016 SR_MHZ(200)
45 #define MAX_SAMPLE_RATE_LA1016 SR_MHZ(100)
46 #define MAX_SAMPLE_DEPTH 10e9
47 #define MAX_PWM_FREQ SR_MHZ(20)
48 #define PWM_CLOCK SR_MHZ(200) /* this is 200MHz for both the LA2016 and LA1016 */
50 /* usb vendor class control requests to the cypress FX2 microcontroller */
51 #define CMD_FPGA_ENABLE 0x10
52 #define CMD_FPGA_SPI 0x20 /* access registers in the FPGA over SPI bus, ctrl_in reads, ctrl_out writes */
53 #define CMD_BULK_START 0x30 /* begin transfer of capture data via usb endpoint 6 IN */
54 #define CMD_BULK_RESET 0x38 /* flush FX2 usb endpoint 6 IN fifos */
55 #define CMD_FPGA_INIT 0x50 /* used before and after FPGA bitstream loading */
56 #define CMD_KAUTH 0x60 /* communicate with authentication ic U10, not used */
57 #define CMD_EEPROM 0xa2 /* ctrl_in reads, ctrl_out writes */
60 * fpga spi register addresses for control request CMD_FPGA_SPI:
61 * There are around 60 byte-wide registers within the fpga and
62 * these are the base addresses used for accessing them.
63 * On the spi bus, the msb of the address byte is set for read
64 * and cleared for write, but that is handled by the fx2 mcu
65 * as appropriate. In this driver code just use IN transactions
66 * to read, OUT to write.
68 #define REG_RUN 0x00 /* read capture status, write capture start */
69 #define REG_PWM_EN 0x02 /* user pwm channels on/off */
70 #define REG_CAPT_MODE 0x03 /* set to 0x00 for capture to sdram, 0x01 bypass sdram for streaming */
71 #define REG_BULK 0x08 /* write start address and number of bytes for capture data bulk upload */
72 #define REG_SAMPLING 0x10 /* write capture config, read capture data location in sdram */
73 #define REG_TRIGGER 0x20 /* write level and edge trigger config */
74 #define REG_THRESHOLD 0x68 /* write two pwm configs to control input threshold dac */
75 #define REG_PWM1 0x70 /* write config for user pwm1 */
76 #define REG_PWM2 0x78 /* write config for user pwm2 */
78 static int ctrl_in(const struct sr_dev_inst *sdi,
79 uint8_t bRequest, uint16_t wValue, uint16_t wIndex,
80 void *data, uint16_t wLength)
82 struct sr_usb_dev_inst *usb;
87 if ((ret = libusb_control_transfer(
88 usb->devhdl, LIBUSB_REQUEST_TYPE_VENDOR | LIBUSB_ENDPOINT_IN,
89 bRequest, wValue, wIndex, (unsigned char *)data, wLength,
90 DEFAULT_TIMEOUT_MS)) != wLength) {
91 sr_err("failed to read %d bytes via ctrl-in %d %#x, %d: %s.",
92 wLength, bRequest, wValue, wIndex,
93 libusb_error_name(ret));
100 static int ctrl_out(const struct sr_dev_inst *sdi,
101 uint8_t bRequest, uint16_t wValue, uint16_t wIndex,
102 void *data, uint16_t wLength)
104 struct sr_usb_dev_inst *usb;
109 if ((ret = libusb_control_transfer(
110 usb->devhdl, LIBUSB_REQUEST_TYPE_VENDOR | LIBUSB_ENDPOINT_OUT,
111 bRequest, wValue, wIndex, (unsigned char*)data, wLength,
112 DEFAULT_TIMEOUT_MS)) != wLength) {
113 sr_err("failed to write %d bytes via ctrl-out %d %#x, %d: %s.",
114 wLength, bRequest, wValue, wIndex,
115 libusb_error_name(ret));
122 static int upload_fpga_bitstream(const struct sr_dev_inst *sdi, const char *bitstream_fname)
124 struct dev_context *devc;
125 struct drv_context *drvc;
126 struct sr_usb_dev_inst *usb;
127 struct sr_resource bitstream;
128 uint8_t buffer[sizeof(uint32_t)];
135 unsigned int zero_pad_to = 0x2c000;
138 drvc = sdi->driver->context;
141 sr_info("Uploading FPGA bitstream '%s'.", bitstream_fname);
143 ret = sr_resource_open(drvc->sr_ctx, &bitstream, SR_RESOURCE_FIRMWARE, bitstream_fname);
145 sr_err("could not find fpga firmware %s!", bitstream_fname);
149 devc->bitstream_size = (uint32_t)bitstream.size;
151 write_u32le_inc(&wrptr, devc->bitstream_size);
152 if ((ret = ctrl_out(sdi, CMD_FPGA_INIT, 0x00, 0, buffer, wrptr - buffer)) != SR_OK) {
153 sr_err("failed to give upload init command");
154 sr_resource_close(drvc->sr_ctx, &bitstream);
160 if (pos < bitstream.size) {
161 len = (int)sr_resource_read(drvc->sr_ctx, &bitstream, &block, sizeof(block));
163 sr_err("failed to read from fpga bitstream!");
164 sr_resource_close(drvc->sr_ctx, &bitstream);
168 // fill with zero's until zero_pad_to
169 len = zero_pad_to - pos;
170 if ((unsigned)len > sizeof(block))
172 memset(&block, 0, len);
177 ret = libusb_bulk_transfer(usb->devhdl, 2, (unsigned char*)&block[0], len, &act_len, DEFAULT_TIMEOUT_MS);
179 sr_dbg("failed to write fpga bitstream block at %#x len %d: %s.", pos, (int)len, libusb_error_name(ret));
183 if (act_len != len) {
184 sr_dbg("failed to write fpga bitstream block at %#x len %d: act_len is %d.", pos, (int)len, act_len);
190 sr_resource_close(drvc->sr_ctx, &bitstream);
193 sr_info("FPGA bitstream upload (%" PRIu64 " bytes) done.", bitstream.size);
195 if ((ret = ctrl_in(sdi, CMD_FPGA_INIT, 0x00, 0, &cmd_resp, sizeof(cmd_resp))) != SR_OK) {
196 sr_err("failed to read response after FPGA bitstream upload");
200 sr_err("after fpga bitstream upload command response is 0x%02x, expect 0!", cmd_resp);
206 if ((ret = ctrl_out(sdi, CMD_FPGA_ENABLE, 0x01, 0, NULL, 0)) != SR_OK) {
207 sr_err("failed enable fpga");
215 static int set_threshold_voltage(const struct sr_dev_inst *sdi, float voltage)
217 struct dev_context *devc;
222 uint16_t duty_R79,duty_R56;
223 uint8_t buf[2 * sizeof(uint16_t)];
226 /* clamp threshold setting within valid range for LA2016 */
230 else if (voltage < -4.0) {
235 * The fpga has two programmable pwm outputs which feed a dac that
236 * is used to adjust input offset. The dac changes the input
237 * swing around the fixed fpga input threshold.
238 * The two pwm outputs can be seen on R79 and R56 respectvely.
239 * Frequency is fixed at 100kHz and duty is varied.
240 * The R79 pwm uses just three settings.
241 * The R56 pwm varies with required threshold and its behaviour
242 * also changes depending on the setting of R79 PWM.
246 * calculate required pwm duty register values from requested threshold voltage
247 * see last page of schematic (on wiki) for an explanation of these numbers
249 if (voltage >= 2.9) {
250 duty_R79 = 0; /* this pwm is off (0V)*/
251 duty_R56 = (uint16_t)(302 * voltage - 363);
253 else if (voltage <= -0.4) {
254 duty_R79 = 0x02D7; /* 72% duty */
255 duty_R56 = (uint16_t)(302 * voltage + 1090);
258 duty_R79 = 0x00f2; /* 25% duty */
259 duty_R56 = (uint16_t)(302 * voltage + 121);
262 /* clamp duty register values at sensible limits */
266 else if (duty_R56 > 1100) {
270 sr_dbg("set threshold voltage %.2fV", voltage);
271 sr_dbg("duty_R56=0x%04x, duty_R79=0x%04x", duty_R56, duty_R79);
274 write_u16le_inc(&wrptr, duty_R56);
275 write_u16le_inc(&wrptr, duty_R79);
277 ret = ctrl_out(sdi, CMD_FPGA_SPI, REG_THRESHOLD, 0, buf, wrptr - buf);
279 sr_err("error setting new threshold voltage of %.2fV", voltage);
282 devc->threshold_voltage = voltage;
287 static int enable_pwm(const struct sr_dev_inst *sdi, uint8_t p1, uint8_t p2)
289 struct dev_context *devc;
296 if (p1) cfg |= 1 << 0;
297 if (p2) cfg |= 1 << 1;
299 sr_dbg("set pwm enable %d %d", p1, p2);
300 ret = ctrl_out(sdi, CMD_FPGA_SPI, REG_PWM_EN, 0, &cfg, sizeof(cfg));
302 sr_err("error setting new pwm enable 0x%02x", cfg);
305 devc->pwm_setting[0].enabled = (p1) ? 1 : 0;
306 devc->pwm_setting[1].enabled = (p2) ? 1 : 0;
311 static int set_pwm(const struct sr_dev_inst *sdi, uint8_t which, float freq, float duty)
313 int CTRL_PWM[] = { REG_PWM1, REG_PWM2 };
314 struct dev_context *devc;
315 pwm_setting_dev_t cfg;
316 pwm_setting_t *setting;
318 uint8_t buf[2 * sizeof(uint32_t)];
323 if (which < 1 || which > 2) {
324 sr_err("invalid pwm channel: %d", which);
327 if (freq > MAX_PWM_FREQ) {
328 sr_err("pwm frequency too high: %.1f", freq);
331 if (duty > 100 || duty < 0) {
332 sr_err("invalid pwm percentage: %f", duty);
336 cfg.period = (uint32_t)(PWM_CLOCK / freq);
337 cfg.duty = (uint32_t)(0.5f + (cfg.period * duty / 100.));
338 sr_dbg("set pwm%d period %d, duty %d", which, cfg.period, cfg.duty);
341 write_u32le_inc(&wrptr, cfg.period);
342 write_u32le_inc(&wrptr, cfg.duty);
343 ret = ctrl_out(sdi, CMD_FPGA_SPI, CTRL_PWM[which - 1], 0, buf, wrptr - buf);
345 sr_err("error setting new pwm%d config %d %d", which, cfg.period, cfg.duty);
348 setting = &devc->pwm_setting[which - 1];
349 setting->freq = freq;
350 setting->duty = duty;
355 static int set_defaults(const struct sr_dev_inst *sdi)
357 struct dev_context *devc;
362 devc->capture_ratio = 5; /* percent */
363 devc->cur_channels = 0xffff;
364 devc->limit_samples = 5000000;
365 devc->cur_samplerate = SR_MHZ(100);
367 ret = set_threshold_voltage(sdi, devc->threshold_voltage);
371 ret = enable_pwm(sdi, 0, 0);
375 ret = set_pwm(sdi, 1, 1e3, 50);
379 ret = set_pwm(sdi, 2, 100e3, 50);
383 ret = enable_pwm(sdi, 1, 1);
390 static int set_trigger_config(const struct sr_dev_inst *sdi)
392 struct dev_context *devc;
393 struct sr_trigger *trigger;
397 struct sr_trigger_stage *stage1;
398 struct sr_trigger_match *match;
401 uint8_t buf[4 * sizeof(uint32_t)];
405 trigger = sr_session_trigger_get(sdi->session);
407 memset(&cfg, 0, sizeof(cfg));
409 cfg.channels = devc->cur_channels;
411 if (trigger && trigger->stages) {
412 stages = trigger->stages;
413 stage1 = stages->data;
415 sr_err("Only one trigger stage supported for now.");
418 channel = stage1->matches;
420 match = channel->data;
421 ch_mask = 1 << match->channel->index;
423 switch (match->match) {
424 case SR_TRIGGER_ZERO:
425 cfg.level |= ch_mask;
426 cfg.high_or_falling &= ~ch_mask;
429 cfg.level |= ch_mask;
430 cfg.high_or_falling |= ch_mask;
432 case SR_TRIGGER_RISING:
433 if ((cfg.enabled & ~cfg.level)) {
434 sr_err("Only one trigger signal with falling-/rising-edge allowed.");
437 cfg.level &= ~ch_mask;
438 cfg.high_or_falling &= ~ch_mask;
440 case SR_TRIGGER_FALLING:
441 if ((cfg.enabled & ~cfg.level)) {
442 sr_err("Only one trigger signal with falling-/rising-edge allowed.");
445 cfg.level &= ~ch_mask;
446 cfg.high_or_falling |= ch_mask;
449 sr_err("Unknown trigger value.");
452 cfg.enabled |= ch_mask;
453 channel = channel->next;
456 sr_dbg("set trigger configuration channels: 0x%04x, "
457 "trigger-enabled 0x%04x, level-triggered 0x%04x, "
458 "high/falling 0x%04x", cfg.channels, cfg.enabled, cfg.level,
459 cfg.high_or_falling);
461 devc->had_triggers_configured = cfg.enabled != 0;
464 write_u32le_inc(&wrptr, cfg.channels);
465 write_u32le_inc(&wrptr, cfg.enabled);
466 write_u32le_inc(&wrptr, cfg.level);
467 write_u32le_inc(&wrptr, cfg.high_or_falling);
468 ret = ctrl_out(sdi, CMD_FPGA_SPI, REG_TRIGGER, 16, buf, wrptr - buf);
470 sr_err("error setting trigger config!");
477 static int set_sample_config(const struct sr_dev_inst *sdi)
479 struct dev_context *devc;
480 double clock_divisor;
484 uint8_t buf[2 * sizeof(uint32_t) + 48 / 8 + sizeof(uint16_t)];
488 total = 128 * 1024 * 1024;
490 if (devc->cur_samplerate > devc->max_samplerate) {
491 sr_err("too high sample rate: %" PRIu64, devc->cur_samplerate);
495 clock_divisor = devc->max_samplerate / (double)devc->cur_samplerate;
496 if (clock_divisor > 0xffff)
497 clock_divisor = 0xffff;
498 divisor = (uint16_t)(clock_divisor + 0.5);
499 devc->cur_samplerate = devc->max_samplerate / divisor;
501 if (devc->limit_samples > MAX_SAMPLE_DEPTH) {
502 sr_err("too high sample depth: %" PRIu64, devc->limit_samples);
506 devc->pre_trigger_size = (devc->capture_ratio * devc->limit_samples) / 100;
508 sr_dbg("set sampling configuration %.0fkHz, %d samples, trigger-pos %d%%",
509 devc->cur_samplerate / 1e3, (unsigned int)devc->limit_samples, (unsigned int)devc->capture_ratio);
512 write_u32le_inc(&wrptr, devc->limit_samples);
513 write_u8_inc(&wrptr, 0);
514 write_u32le_inc(&wrptr, devc->pre_trigger_size);
515 write_u32le_inc(&wrptr, ((total * devc->capture_ratio) / 100) & 0xFFFFFF00);
516 write_u16le_inc(&wrptr, divisor);
517 write_u8_inc(&wrptr, 0);
519 ret = ctrl_out(sdi, CMD_FPGA_SPI, REG_SAMPLING, 0, buf, wrptr - buf);
521 sr_err("error setting sample config!");
528 /* The run state is read from FPGA registers 1[hi-byte] and 0[lo-byte]
529 * and the bits are interpreted as follows:
533 * bit1 1= writing to sdram
534 * bit2 0= waiting_for_trigger 1=been_triggered
535 * bit3 0= pretrigger_sampling 1=posttrigger_sampling
538 * meaning of bits unknown (but vendor software reads this, so just do the same)
540 * The run state values occur in this order:
541 * 0x85E2: pre-sampling (for samples before trigger position, capture ratio > 0%)
542 * 0x85EA: pre-sampling complete, now waiting for trigger (whilst sampling continuously)
546 static uint16_t run_state(const struct sr_dev_inst *sdi)
549 static uint16_t previous_state = 0;
552 if ((ret = ctrl_in(sdi, CMD_FPGA_SPI, REG_RUN, 0, &state, sizeof(state))) != SR_OK) {
553 sr_err("failed to read run state!");
557 /* This function is called about every 50ms.
558 * To avoid filling the log file with redundant information during long captures,
559 * just print a log message if status has changed.
562 if (state != previous_state) {
563 previous_state = state;
564 if ((state & 0x0003) == 0x01) {
565 sr_dbg("run_state: 0x%04x (%s)", state, "idle");
567 else if ((state & 0x000f) == 0x02) {
568 sr_dbg("run_state: 0x%04x (%s)", state, "pre-trigger sampling");
570 else if ((state & 0x000f) == 0x0a) {
571 sr_dbg("run_state: 0x%04x (%s)", state, "sampling, waiting for trigger");
573 else if ((state & 0x000f) == 0x0e) {
574 sr_dbg("run_state: 0x%04x (%s)", state, "post-trigger sampling");
577 sr_dbg("run_state: 0x%04x", state);
584 static int set_run_mode(const struct sr_dev_inst *sdi, uint8_t fast_blinking)
588 if ((ret = ctrl_out(sdi, CMD_FPGA_SPI, REG_RUN, 0, &fast_blinking, sizeof(fast_blinking))) != SR_OK) {
589 sr_err("failed to send set-run-mode command %d", fast_blinking);
596 static int get_capture_info(const struct sr_dev_inst *sdi)
598 struct dev_context *devc;
600 uint8_t buf[3 * sizeof(uint32_t)];
601 const uint8_t *rdptr;
605 if ((ret = ctrl_in(sdi, CMD_FPGA_SPI, REG_SAMPLING, 0, buf, sizeof(buf))) != SR_OK) {
606 sr_err("failed to read capture info!");
611 devc->info.n_rep_packets = read_u32le_inc(&rdptr);
612 devc->info.n_rep_packets_before_trigger = read_u32le_inc(&rdptr);
613 devc->info.write_pos = read_u32le_inc(&rdptr);
615 sr_dbg("capture info: n_rep_packets: 0x%08x/%d, before_trigger: 0x%08x/%d, write_pos: 0x%08x%d",
616 devc->info.n_rep_packets, devc->info.n_rep_packets,
617 devc->info.n_rep_packets_before_trigger, devc->info.n_rep_packets_before_trigger,
618 devc->info.write_pos, devc->info.write_pos);
620 if (devc->info.n_rep_packets % 5)
621 sr_warn("number of packets is not as expected multiples of 5: %d", devc->info.n_rep_packets);
626 SR_PRIV int la2016_upload_firmware(struct sr_context *sr_ctx, libusb_device *dev, uint16_t product_id)
629 snprintf(fw_file, sizeof(fw_file) - 1, UC_FIRMWARE, product_id);
630 return ezusb_upload_firmware(sr_ctx, dev, USB_CONFIGURATION, fw_file);
633 SR_PRIV int la2016_setup_acquisition(const struct sr_dev_inst *sdi)
635 struct dev_context *devc;
641 ret = set_threshold_voltage(sdi, devc->threshold_voltage);
646 if ((ret = ctrl_out(sdi, CMD_FPGA_SPI, REG_CAPT_MODE, 0, &cmd, sizeof(cmd))) != SR_OK) {
647 sr_err("failed to send stop sampling command");
651 ret = set_trigger_config(sdi);
655 ret = set_sample_config(sdi);
662 SR_PRIV int la2016_start_acquisition(const struct sr_dev_inst *sdi)
666 ret = set_run_mode(sdi, 3);
673 static int la2016_stop_acquisition(const struct sr_dev_inst *sdi)
677 ret = set_run_mode(sdi, 0);
684 SR_PRIV int la2016_abort_acquisition(const struct sr_dev_inst *sdi)
687 struct dev_context *devc;
689 ret = la2016_stop_acquisition(sdi);
693 devc = sdi ? sdi->priv : NULL;
694 if (devc && devc->transfer)
695 libusb_cancel_transfer(devc->transfer);
700 static int la2016_has_triggered(const struct sr_dev_inst *sdi)
704 state = run_state(sdi);
706 return (state & 0x3) == 1;
709 static int la2016_start_retrieval(const struct sr_dev_inst *sdi, libusb_transfer_cb_fn cb)
711 struct dev_context *devc;
712 struct sr_usb_dev_inst *usb;
714 uint8_t wrbuf[2 * sizeof(uint32_t)];
722 if ((ret = get_capture_info(sdi)) != SR_OK)
725 devc->n_transfer_packets_to_read = devc->info.n_rep_packets / NUM_PACKETS_IN_CHUNK;
726 devc->n_bytes_to_read = devc->n_transfer_packets_to_read * TRANSFER_PACKET_LENGTH;
727 devc->read_pos = devc->info.write_pos - devc->n_bytes_to_read;
728 devc->n_reps_until_trigger = devc->info.n_rep_packets_before_trigger;
730 sr_dbg("want to read %d tfer-packets starting from pos %d",
731 devc->n_transfer_packets_to_read, devc->read_pos);
733 if ((ret = ctrl_out(sdi, CMD_BULK_RESET, 0x00, 0, NULL, 0)) != SR_OK) {
734 sr_err("failed to reset bulk state");
737 sr_dbg("will read from 0x%08x, 0x%08x bytes", devc->read_pos, devc->n_bytes_to_read);
739 write_u32le_inc(&wrptr, devc->read_pos);
740 write_u32le_inc(&wrptr, devc->n_bytes_to_read);
741 if ((ret = ctrl_out(sdi, CMD_FPGA_SPI, REG_BULK, 0, wrbuf, wrptr - wrbuf)) != SR_OK) {
742 sr_err("failed to send bulk config");
745 if ((ret = ctrl_out(sdi, CMD_BULK_START, 0x00, 0, NULL, 0)) != SR_OK) {
746 sr_err("failed to unblock bulk transfers");
750 to_read = devc->n_bytes_to_read;
751 /* choose a buffer size for all of the usb transfers */
752 if (to_read >= LA2016_USB_BUFSZ)
753 to_read = LA2016_USB_BUFSZ; /* multiple transfers */
754 else /* one transfer, make buffer size some multiple of LA2016_EP6_PKTSZ */
755 to_read = (to_read + (LA2016_EP6_PKTSZ-1)) & ~(LA2016_EP6_PKTSZ-1);
756 buffer = g_try_malloc(to_read);
758 sr_err("Failed to allocate %d bytes for bulk transfer", to_read);
759 return SR_ERR_MALLOC;
762 devc->transfer = libusb_alloc_transfer(0);
763 libusb_fill_bulk_transfer(
764 devc->transfer, usb->devhdl,
765 0x86, buffer, to_read,
766 cb, (void *)sdi, DEFAULT_TIMEOUT_MS);
768 if ((ret = libusb_submit_transfer(devc->transfer)) != 0) {
769 sr_err("Failed to submit transfer: %s.", libusb_error_name(ret));
770 libusb_free_transfer(devc->transfer);
771 devc->transfer = NULL;
779 static void send_chunk(struct sr_dev_inst *sdi,
780 const uint8_t *packets, unsigned int num_tfers)
782 struct dev_context *devc;
783 struct sr_datafeed_logic logic;
784 struct sr_datafeed_packet sr_packet;
785 unsigned int max_samples, n_samples, total_samples, free_n_samples;
786 unsigned int i, j, k;
787 int do_signal_trigger;
796 logic.data = devc->convbuffer;
798 sr_packet.type = SR_DF_LOGIC;
799 sr_packet.payload = &logic;
801 max_samples = devc->convbuffer_size / 2;
803 wp = (uint16_t *)devc->convbuffer;
805 do_signal_trigger = 0;
807 if (devc->had_triggers_configured && devc->reading_behind_trigger == 0 && devc->info.n_rep_packets_before_trigger == 0) {
808 std_session_send_df_trigger(sdi);
809 devc->reading_behind_trigger = 1;
813 for (i = 0; i < num_tfers; i++) {
814 for (k = 0; k < NUM_PACKETS_IN_CHUNK; k++) {
815 free_n_samples = max_samples - n_samples;
816 if (free_n_samples < 256 || do_signal_trigger) {
817 logic.length = n_samples * 2;
818 sr_session_send(sdi, &sr_packet);
820 wp = (uint16_t *)devc->convbuffer;
821 if (do_signal_trigger) {
822 std_session_send_df_trigger(sdi);
823 do_signal_trigger = 0;
827 state = read_u16le_inc(&rp);
828 repetitions = read_u8_inc(&rp);
829 for (j = 0; j < repetitions; j++)
832 n_samples += repetitions;
833 total_samples += repetitions;
834 devc->total_samples += repetitions;
835 if (!devc->reading_behind_trigger) {
836 devc->n_reps_until_trigger--;
837 if (devc->n_reps_until_trigger == 0) {
838 devc->reading_behind_trigger = 1;
839 do_signal_trigger = 1;
840 sr_dbg(" here is trigger position after %" PRIu64 " samples, %.6fms",
842 (double)devc->total_samples / devc->cur_samplerate * 1e3);
846 (void)read_u8_inc(&rp); /* Skip sequence number. */
849 logic.length = n_samples * 2;
850 sr_session_send(sdi, &sr_packet);
851 if (do_signal_trigger) {
852 std_session_send_df_trigger(sdi);
855 sr_dbg("send_chunk done after %d samples", total_samples);
858 static void LIBUSB_CALL receive_transfer(struct libusb_transfer *transfer)
860 struct sr_dev_inst *sdi;
861 struct dev_context *devc;
862 struct sr_usb_dev_inst *usb;
865 sdi = transfer->user_data;
869 sr_dbg("receive_transfer(): status %s received %d bytes.",
870 libusb_error_name(transfer->status), transfer->actual_length);
872 if (transfer->status == LIBUSB_TRANSFER_TIMED_OUT) {
873 sr_err("bulk transfer timeout!");
874 devc->transfer_finished = 1;
876 send_chunk(sdi, transfer->buffer, transfer->actual_length / TRANSFER_PACKET_LENGTH);
878 devc->n_bytes_to_read -= transfer->actual_length;
879 if (devc->n_bytes_to_read) {
880 uint32_t to_read = devc->n_bytes_to_read;
881 /* determine read size for the next usb transfer */
882 if (to_read >= LA2016_USB_BUFSZ)
883 to_read = LA2016_USB_BUFSZ;
884 else /* last transfer, make read size some multiple of LA2016_EP6_PKTSZ */
885 to_read = (to_read + (LA2016_EP6_PKTSZ-1)) & ~(LA2016_EP6_PKTSZ-1);
886 libusb_fill_bulk_transfer(
887 transfer, usb->devhdl,
888 0x86, transfer->buffer, to_read,
889 receive_transfer, (void *)sdi, DEFAULT_TIMEOUT_MS);
891 if ((ret = libusb_submit_transfer(transfer)) == 0)
893 sr_err("Failed to submit further transfer: %s.", libusb_error_name(ret));
896 g_free(transfer->buffer);
897 libusb_free_transfer(transfer);
898 devc->transfer_finished = 1;
901 SR_PRIV int la2016_receive_data(int fd, int revents, void *cb_data)
903 const struct sr_dev_inst *sdi;
904 struct dev_context *devc;
905 struct drv_context *drvc;
913 drvc = sdi->driver->context;
915 if (devc->have_trigger == 0) {
916 if (la2016_has_triggered(sdi) == 0) {
917 /* not yet ready for download */
920 devc->have_trigger = 1;
921 devc->transfer_finished = 0;
922 devc->reading_behind_trigger = 0;
923 devc->total_samples = 0;
924 /* we can start retrieving data! */
925 if (la2016_start_retrieval(sdi, receive_transfer) != SR_OK) {
926 sr_err("failed to start retrieval!");
929 sr_dbg("retrieval is started...");
930 std_session_send_df_frame_begin(sdi);
935 tv.tv_sec = tv.tv_usec = 0;
936 libusb_handle_events_timeout(drvc->sr_ctx->libusb_ctx, &tv);
938 if (devc->transfer_finished) {
939 sr_dbg("transfer is finished!");
940 std_session_send_df_frame_end(sdi);
942 usb_source_remove(sdi->session, drvc->sr_ctx);
943 std_session_send_df_end(sdi);
945 la2016_stop_acquisition(sdi);
947 g_free(devc->convbuffer);
948 devc->convbuffer = NULL;
950 devc->transfer = NULL;
952 sr_dbg("transfer is now finished");
958 SR_PRIV int la2016_init_device(const struct sr_dev_inst *sdi)
960 struct dev_context *devc;
963 int16_t purchase_date_bcd[2];
969 /* Four bytes of eeprom at 0x20 are purchase year & month in BCD format, with 16bit
970 * complemented checksum; e.g. 2004DFFB = 2020-April.
971 * This helps to identify the age of devices if unknown magic numbers occur.
973 if ((ret = ctrl_in(sdi, CMD_EEPROM, 0x20, 0, purchase_date_bcd, sizeof(purchase_date_bcd))) != SR_OK) {
974 sr_err("failed to read eeprom purchase_date_bcd");
977 sr_dbg("purchase date: 20%02hx-%02hx", (purchase_date_bcd[0]) & 0x00ff, (purchase_date_bcd[0] >> 8) & 0x00ff);
978 if (purchase_date_bcd[0] != (0x0ffff & ~purchase_date_bcd[1])) {
979 sr_err("purchase date: checksum failure");
984 * There are four known kingst logic analyser devices which use this same usb vid and pid:
985 * LA2016, LA1016 and the older revision of each of these. They all use the same hardware
986 * and the same FX2 mcu firmware but each requires a different fpga bitstream. They are
987 * differentiated by a 'magic' byte within the 8 bytes of EEPROM from address 0x08.
998 * It seems that only these magic bytes are used, other bytes shown above are 'don't care'.
999 * Changing the magic byte on newer device to older magic causes OEM software to load
1000 * the older fpga bitstream. The device then functions but has channels out of order.
1001 * It's likely the bitstreams were changed to move input channel pins due to PCB changes.
1003 * magic 9 == LA1016a using "kingst-la1016a1-fpga.bitstream" (latest v1.3.0 PCB, perhaps others)
1004 * magic 8 == LA2016a using "kingst-la2016a1-fpga.bitstream" (latest v1.3.0 PCB, perhaps others)
1005 * magic 3 == LA1016 using "kingst-la1016-fpga.bitstream"
1006 * magic 2 == LA2016 using "kingst-la2016-fpga.bitstream"
1008 * This was all determined by altering the eeprom contents of an LA2016 and LA1016 and observing
1009 * the vendor software actions, either raising errors or loading specific bitstreams.
1012 * An LA1016 cannot be converted to an LA2016 by changing the magic number - the bitstream
1013 * will not authenticate with ic U10, which has different security coding for each device type.
1016 if ((ret = ctrl_in(sdi, CMD_EEPROM, 0x08, 0, &buf, sizeof(buf))) != SR_OK) {
1017 sr_err("failed to read eeprom device identifier bytes");
1022 if (buf[0] == (0x0ff & ~buf[1])) {
1023 /* primary copy of magic passes complement check */
1026 else if (buf[4] == (0x0ff & ~buf[5])) {
1027 /* backup copy of magic passes complement check */
1028 sr_dbg("device_type: using backup copy of magic number");
1032 sr_dbg("device_type: magic number is %hhu", magic);
1034 /* select the correct fpga bitstream for this device */
1037 ret = upload_fpga_bitstream(sdi, FPGA_FW_LA2016);
1038 devc->max_samplerate = MAX_SAMPLE_RATE_LA2016;
1041 ret = upload_fpga_bitstream(sdi, FPGA_FW_LA1016);
1042 devc->max_samplerate = MAX_SAMPLE_RATE_LA1016;
1045 ret = upload_fpga_bitstream(sdi, FPGA_FW_LA2016A);
1046 devc->max_samplerate = MAX_SAMPLE_RATE_LA2016;
1049 ret = upload_fpga_bitstream(sdi, FPGA_FW_LA1016A);
1050 devc->max_samplerate = MAX_SAMPLE_RATE_LA1016;
1053 sr_err("device_type: device not supported; magic number indicates this is not a LA2016 or LA1016");
1058 sr_err("failed to upload fpga bitstream");
1062 state = run_state(sdi);
1063 if (state != 0x85e9) {
1064 sr_warn("expect run state to be 0x85e9, but it reads 0x%04x", state);
1067 if ((ret = ctrl_out(sdi, CMD_BULK_RESET, 0x00, 0, NULL, 0)) != SR_OK) {
1068 sr_err("failed to send CMD_BULK_RESET");
1072 sr_dbg("device should be initialized");
1074 return set_defaults(sdi);
1077 SR_PRIV int la2016_deinit_device(const struct sr_dev_inst *sdi)
1081 if ((ret = ctrl_out(sdi, CMD_FPGA_ENABLE, 0x00, 0, NULL, 0)) != SR_OK) {
1082 sr_err("failed to send deinit command");