2 * This file is part of the libsigrok project.
4 * Copyright (C) 2022 Gerhard Sittig <gerhard.sittig@gmx.net>
5 * Copyright (C) 2020 Florian Schmidt <schmidt_florian@gmx.de>
6 * Copyright (C) 2013 Marcus Comstedt <marcus@mc.pp.se>
7 * Copyright (C) 2013 Bert Vermeulen <bert@biot.com>
8 * Copyright (C) 2012 Joel Holdsworth <joel@airwebreathe.org.uk>
10 * This program is free software: you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation, either version 3 of the License, or
13 * (at your option) any later version.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program. If not, see <http://www.gnu.org/licenses/>.
26 #include <libsigrok/libsigrok.h>
29 #include "libsigrok-internal.h"
32 /* USB PID dependent MCU firmware. Model dependent FPGA bitstream. */
33 #define MCU_FWFILE_FMT "kingst-la-%04x.fw"
34 #define FPGA_FWFILE_FMT "kingst-%s-fpga.bitstream"
37 * List of known devices and their features. See @ref kingst_model
38 * for the fields' type and meaning. Table is sorted by EEPROM magic.
39 * More specific items need to go first (additional byte[2/6]). Not
40 * all devices are covered by this driver implementation, but telling
41 * users what was detected is considered useful.
43 * TODO Verify the identification of models that were not tested before.
45 static const struct kingst_model models[] = {
46 { 0x02, 0x01, "LA2016", "la2016a1", SR_MHZ(200), 16, 1, 0, },
47 { 0x02, 0x00, "LA2016", "la2016", SR_MHZ(200), 16, 1, 0, },
48 { 0x03, 0x01, "LA1016", "la1016a1", SR_MHZ(100), 16, 1, 0, },
49 { 0x03, 0x00, "LA1016", "la1016", SR_MHZ(100), 16, 1, 0, },
50 { 0x04, 0x00, "LA1010", "la1010a0", SR_MHZ(100), 16, 0, SR_MHZ(800), },
51 { 0x05, 0x00, "LA5016", "la5016a1", SR_MHZ(500), 16, 2, SR_MHZ(800), },
52 { 0x06, 0x00, "LA5032", "la5032a0", SR_MHZ(500), 32, 4, SR_MHZ(800), },
53 { 0x07, 0x00, "LA1010", "la1010a1", SR_MHZ(100), 16, 0, SR_MHZ(800), },
54 { 0x08, 0x00, "LA2016", "la2016a1", SR_MHZ(200), 16, 1, 0, },
55 { 0x09, 0x00, "LA1016", "la1016a1", SR_MHZ(100), 16, 1, 0, },
56 { 0x0a, 0x00, "LA1010", "la1010a2", SR_MHZ(100), 16, 0, SR_MHZ(800), },
57 { 0x0c, 0x10, "LA5016", "la5016a2", SR_MHZ(500), 16, 2, SR_MHZ(800), },
58 { 0x0c, 0x00, "LA5016", "la5016a2", SR_MHZ(500), 16, 2, SR_MHZ(800), },
59 { 0x41, 0x00, "LA5016", "la5016a1", SR_MHZ(500), 16, 2, SR_MHZ(800), },
62 /* USB vendor class control requests, executed by the Cypress FX2 MCU. */
63 #define CMD_FPGA_ENABLE 0x10
64 #define CMD_FPGA_SPI 0x20 /* R/W access to FPGA registers via SPI. */
65 #define CMD_BULK_START 0x30 /* Start sample data download via USB EP6 IN. */
66 #define CMD_BULK_RESET 0x38 /* Flush FIFO of FX2 USB EP6 IN. */
67 #define CMD_FPGA_INIT 0x50 /* Used before and after FPGA bitstream upload. */
68 #define CMD_KAUTH 0x60 /* Communicate to auth IC (U10). Not used. */
69 #define CMD_EEPROM 0xa2 /* R/W access to EEPROM content. */
72 * FPGA register addresses (base addresses when registers span multiple
73 * bytes, in that case data is kept in little endian format). Passed to
74 * CMD_FPGA_SPI requests. The FX2 MCU transparently handles the detail
75 * of SPI transfers encoding the read (1) or write (0) direction in the
76 * MSB of the address field. There are some 60 byte-wide FPGA registers.
78 * Unfortunately the FPGA registers change their meaning between the
79 * read and write directions of access, or exclusively provide one of
80 * these directions and not the other. This is an arbitrary vendor's
81 * choice, there is nothing which the sigrok driver could do about it.
82 * Values written to registers typically cannot get read back, neither
83 * verified after writing a configuration, nor queried upon startup for
84 * automatic detection of the current configuration. Neither appear to
85 * be there echo registers for presence and communication checks, nor
86 * version identifying registers, as far as we know.
88 #define REG_RUN 0x00 /* Read capture status, write start capture. */
89 #define REG_PWM_EN 0x02 /* User PWM channels on/off. */
90 #define REG_CAPT_MODE 0x03 /* Write 0x00 capture to SDRAM, 0x01 streaming. */
91 #define REG_PIN_STATE 0x04 /* Read current pin state (real time display). */
92 #define REG_BULK 0x08 /* Write start addr, byte count to download samples. */
93 #define REG_SAMPLING 0x10 /* Write capture config, read capture SDRAM location. */
94 #define REG_TRIGGER 0x20 /* Write level and edge trigger config. */
95 #define REG_UNKNOWN_30 0x30
96 #define REG_THRESHOLD 0x68 /* Write PWM config to setup input threshold DAC. */
97 #define REG_PWM1 0x70 /* Write config for user PWM1. */
98 #define REG_PWM2 0x78 /* Write config for user PWM2. */
100 /* Bit patterns to write to REG_CAPT_MODE. */
101 #define CAPTMODE_TO_RAM 0x00
102 #define CAPTMODE_STREAM 0x01
104 /* Bit patterns to write to REG_RUN, setup run mode. */
105 #define RUNMODE_HALT 0x00
106 #define RUNMODE_RUN 0x03
108 /* Bit patterns when reading from REG_RUN, get run state. */
109 #define RUNSTATE_IDLE_BIT (1UL << 0)
110 #define RUNSTATE_DRAM_BIT (1UL << 1)
111 #define RUNSTATE_TRGD_BIT (1UL << 2)
112 #define RUNSTATE_POST_BIT (1UL << 3)
114 static int ctrl_in(const struct sr_dev_inst *sdi,
115 uint8_t bRequest, uint16_t wValue, uint16_t wIndex,
116 void *data, uint16_t wLength)
118 struct sr_usb_dev_inst *usb;
123 ret = libusb_control_transfer(usb->devhdl,
124 LIBUSB_REQUEST_TYPE_VENDOR | LIBUSB_ENDPOINT_IN,
125 bRequest, wValue, wIndex, data, wLength,
127 if (ret != wLength) {
128 sr_dbg("USB ctrl in: %d bytes, req %d val %#x idx %d: %s.",
129 wLength, bRequest, wValue, wIndex,
130 libusb_error_name(ret));
131 sr_err("Cannot read %d bytes from USB: %s.",
132 wLength, libusb_error_name(ret));
139 static int ctrl_out(const struct sr_dev_inst *sdi,
140 uint8_t bRequest, uint16_t wValue, uint16_t wIndex,
141 void *data, uint16_t wLength)
143 struct sr_usb_dev_inst *usb;
148 ret = libusb_control_transfer(usb->devhdl,
149 LIBUSB_REQUEST_TYPE_VENDOR | LIBUSB_ENDPOINT_OUT,
150 bRequest, wValue, wIndex, data, wLength,
152 if (ret != wLength) {
153 sr_dbg("USB ctrl out: %d bytes, req %d val %#x idx %d: %s.",
154 wLength, bRequest, wValue, wIndex,
155 libusb_error_name(ret));
156 sr_err("Cannot write %d bytes to USB: %s.",
157 wLength, libusb_error_name(ret));
164 /* HACK Experiment to spot FPGA registers of interest. */
165 static void la2016_dump_fpga_registers(const struct sr_dev_inst *sdi,
166 const char *caption, size_t reg_lower, size_t reg_upper)
168 static const size_t dump_chunk_len = 16;
171 uint8_t rdbuf[0x80 - 0x00]; /* Span all FPGA registers. */
172 const uint8_t *rdptr;
174 size_t dump_addr, indent, dump_len;
177 if (sr_log_loglevel_get() < SR_LOG_SPEW)
180 if (!reg_lower && !reg_upper) {
182 reg_upper = sizeof(rdbuf);
184 if (reg_upper - reg_lower > sizeof(rdbuf))
185 reg_upper = sizeof(rdbuf) - reg_lower;
187 rdlen = reg_upper - reg_lower;
188 ret = ctrl_in(sdi, CMD_FPGA_SPI, reg_lower, 0, rdbuf, rdlen);
190 sr_err("Cannot get registers space.");
195 sr_spew("FPGA registers dump: %s", caption ? : "for fun");
196 dump_addr = reg_lower;
199 indent = dump_addr % dump_chunk_len;
200 if (dump_len > dump_chunk_len)
201 dump_len = dump_chunk_len;
202 if (dump_len + indent > dump_chunk_len)
203 dump_len = dump_chunk_len - indent;
204 txt = sr_hexdump_new(rdptr, dump_len);
205 sr_spew(" %04zx %*s%s",
206 dump_addr, (int)(3 * indent), "", txt->str);
207 sr_hexdump_free(txt);
208 dump_addr += dump_len;
215 * Check the necessity for FPGA bitstream upload, because another upload
216 * would take some 600ms which is undesirable after program startup. Try
217 * to access some FPGA registers and check the values' plausibility. The
218 * check should fail on the safe side, request another upload when in
219 * doubt. A positive response (the request to continue operation with the
220 * currently active bitstream) should be conservative. Accessing multiple
221 * registers is considered cheap compared to the cost of bitstream upload.
223 * It helps though that both the vendor software and the sigrok driver
224 * use the same bundle of MCU firmware and FPGA bitstream for any of the
225 * supported models. We don't expect to successfully communicate to the
226 * device yet disagree on its protocol. Ideally we would access version
227 * identifying registers for improved robustness, but are not aware of
228 * any. A bitstream reload can always be forced by a power cycle.
230 static int check_fpga_bitstream(const struct sr_dev_inst *sdi)
233 uint8_t buff[REG_PWM_EN - REG_RUN]; /* Larger of REG_RUN, REG_PWM_EN. */
238 const uint8_t *rdptr;
240 sr_dbg("Checking operation of the FPGA bitstream.");
241 la2016_dump_fpga_registers(sdi, "bitstream check", 0, 0);
244 ret = ctrl_in(sdi, CMD_FPGA_INIT, 0x00, 0, &init_rsp, sizeof(init_rsp));
245 if (ret != SR_OK || init_rsp != 0) {
246 sr_dbg("FPGA init query failed, or unexpected response.");
250 read_len = sizeof(run_state);
251 ret = ctrl_in(sdi, CMD_FPGA_SPI, REG_RUN, 0, buff, read_len);
253 sr_dbg("FPGA register access failed (run state).");
257 run_state = read_u16le_inc(&rdptr);
258 sr_spew("FPGA register: run state 0x%04x.", run_state);
259 if (run_state && (run_state & 0x3) != 0x1) {
260 sr_dbg("Unexpected FPGA register content (run state).");
263 if (run_state && (run_state & ~0xf) != 0x85e0) {
264 sr_dbg("Unexpected FPGA register content (run state).");
268 read_len = sizeof(pwm_en);
269 ret = ctrl_in(sdi, CMD_FPGA_SPI, REG_PWM_EN, 0, buff, read_len);
271 sr_dbg("FPGA register access failed (PWM enable).");
275 pwm_en = read_u8_inc(&rdptr);
276 sr_spew("FPGA register: PWM enable 0x%02x.", pwm_en);
277 if ((pwm_en & 0x3) != 0x0) {
278 sr_dbg("Unexpected FPGA register content (PWM enable).");
282 sr_info("Could re-use current FPGA bitstream. No upload required.");
286 static int upload_fpga_bitstream(const struct sr_dev_inst *sdi,
287 const char *bitstream_fname)
289 struct drv_context *drvc;
290 struct sr_usb_dev_inst *usb;
291 struct sr_resource bitstream;
292 uint32_t bitstream_size;
293 uint8_t buffer[sizeof(uint32_t)];
299 unsigned int zero_pad_to;
301 drvc = sdi->driver->context;
304 sr_info("Uploading FPGA bitstream '%s'.", bitstream_fname);
306 ret = sr_resource_open(drvc->sr_ctx, &bitstream,
307 SR_RESOURCE_FIRMWARE, bitstream_fname);
309 sr_err("Cannot find FPGA bitstream %s.", bitstream_fname);
313 bitstream_size = (uint32_t)bitstream.size;
315 write_u32le_inc(&wrptr, bitstream_size);
316 ret = ctrl_out(sdi, CMD_FPGA_INIT, 0x00, 0, buffer, wrptr - buffer);
318 sr_err("Cannot initiate FPGA bitstream upload.");
319 sr_resource_close(drvc->sr_ctx, &bitstream);
322 zero_pad_to = bitstream_size;
323 zero_pad_to += LA2016_EP2_PADDING - 1;
324 zero_pad_to /= LA2016_EP2_PADDING;
325 zero_pad_to *= LA2016_EP2_PADDING;
329 if (pos < bitstream.size) {
330 len = (int)sr_resource_read(drvc->sr_ctx, &bitstream,
331 block, sizeof(block));
333 sr_err("Cannot read FPGA bitstream.");
334 sr_resource_close(drvc->sr_ctx, &bitstream);
338 /* Zero-pad until 'zero_pad_to'. */
339 len = zero_pad_to - pos;
340 if ((unsigned)len > sizeof(block))
342 memset(&block, 0, len);
347 ret = libusb_bulk_transfer(usb->devhdl, USB_EP_FPGA_BITSTREAM,
348 &block[0], len, &act_len, DEFAULT_TIMEOUT_MS);
350 sr_dbg("Cannot write FPGA bitstream, block %#x len %d: %s.",
351 pos, (int)len, libusb_error_name(ret));
355 if (act_len != len) {
356 sr_dbg("Short write for FPGA bitstream, block %#x len %d: got %d.",
357 pos, (int)len, act_len);
363 sr_resource_close(drvc->sr_ctx, &bitstream);
366 sr_info("FPGA bitstream upload (%" PRIu64 " bytes) done.",
372 static int enable_fpga_bitstream(const struct sr_dev_inst *sdi)
377 ret = ctrl_in(sdi, CMD_FPGA_INIT, 0x00, 0, &resp, sizeof(resp));
379 sr_err("Cannot read response after FPGA bitstream upload.");
383 sr_err("Unexpected FPGA bitstream upload response, got 0x%02x, want 0.",
389 ret = ctrl_out(sdi, CMD_FPGA_ENABLE, 0x01, 0, NULL, 0);
391 sr_err("Cannot enable FPGA after bitstream upload.");
399 static int set_threshold_voltage(const struct sr_dev_inst *sdi, float voltage)
402 uint16_t duty_R79, duty_R56;
403 uint8_t buf[REG_PWM1 - REG_THRESHOLD]; /* Width of REG_THRESHOLD. */
406 /* Clamp threshold setting to valid range for LA2016. */
407 if (voltage > LA2016_THR_VOLTAGE_MAX) {
408 voltage = LA2016_THR_VOLTAGE_MAX;
409 } else if (voltage < -LA2016_THR_VOLTAGE_MAX) {
410 voltage = -LA2016_THR_VOLTAGE_MAX;
414 * Two PWM output channels feed one DAC which generates a bias
415 * voltage, which offsets the input probe's voltage level, and
416 * in combination with the FPGA pins' fixed threshold result in
417 * a programmable input threshold from the user's perspective.
418 * The PWM outputs can be seen on R79 and R56 respectively, the
419 * frequency is 100kHz and the duty cycle varies. The R79 PWM
420 * uses three discrete settings. The R56 PWM varies with desired
421 * thresholds and depends on the R79 PWM configuration. See the
422 * schematics comments which discuss the formulae.
424 if (voltage >= 2.9) {
425 duty_R79 = 0; /* PWM off (0V). */
426 duty_R56 = (uint16_t)(302 * voltage - 363);
427 } else if (voltage > -0.4) {
428 duty_R79 = 0x00f2; /* 25% duty cycle. */
429 duty_R56 = (uint16_t)(302 * voltage + 121);
431 duty_R79 = 0x02d7; /* 72% duty cycle. */
432 duty_R56 = (uint16_t)(302 * voltage + 1090);
435 /* Clamp duty register values to sensible limits. */
438 } else if (duty_R56 > 1100) {
442 sr_dbg("Set threshold voltage %.2fV.", voltage);
443 sr_dbg("Duty cycle values: R56 0x%04x, R79 0x%04x.", duty_R56, duty_R79);
446 write_u16le_inc(&wrptr, duty_R56);
447 write_u16le_inc(&wrptr, duty_R79);
449 ret = ctrl_out(sdi, CMD_FPGA_SPI, REG_THRESHOLD, 0, buf, wrptr - buf);
451 sr_err("Cannot set threshold voltage %.2fV.", voltage);
459 * Communicates a channel's configuration to the device after the
460 * parameters may have changed. Configuration of one channel may
461 * interfere with other channels since they share FPGA registers.
463 static int set_pwm_config(const struct sr_dev_inst *sdi, size_t idx)
465 static uint8_t reg_bases[] = { REG_PWM1, REG_PWM2, };
467 struct dev_context *devc;
468 struct pwm_setting *params;
472 uint32_t period, duty;
475 uint8_t enable_all, enable_cfg, reg_val;
476 uint8_t buf[REG_PWM2 - REG_PWM1]; /* Width of one REG_PWMx. */
480 if (idx >= ARRAY_SIZE(devc->pwm_setting))
482 params = &devc->pwm_setting[idx];
483 if (idx >= ARRAY_SIZE(reg_bases))
485 reg_base = reg_bases[idx];
488 * Map application's specs to hardware register values. Do math
489 * in floating point initially, but convert to u32 eventually.
491 sr_dbg("PWM config, app spec, ch %zu, en %d, freq %.1f, duty %.1f.",
492 idx, params->enabled ? 1 : 0, params->freq, params->duty);
494 val_f /= params->freq;
498 val_f *= params->duty;
503 sr_dbg("PWM config, reg 0x%04x, freq %u, duty %u.",
504 (unsigned)reg_base, (unsigned)period, (unsigned)duty);
506 /* Get the "enabled" state of all supported PWM channels. */
508 for (ch = 0; ch < ARRAY_SIZE(devc->pwm_setting); ch++) {
509 if (!devc->pwm_setting[ch].enabled)
511 enable_all |= 1U << ch;
513 enable_cfg = 1U << idx;
514 sr_spew("PWM config, enable all 0x%02hhx, cfg 0x%02hhx.",
515 enable_all, enable_cfg);
518 * Disable the to-get-configured channel before its parameters
519 * will change. Or disable and exit when the channel is supposed
522 sr_spew("PWM config, disabling before param change.");
523 reg_val = enable_all & ~enable_cfg;
524 ret = ctrl_out(sdi, CMD_FPGA_SPI, REG_PWM_EN, 0,
525 ®_val, sizeof(reg_val));
527 sr_err("Cannot adjust PWM enabled state.");
530 if (!params->enabled)
533 /* Write register values to device. */
534 sr_spew("PWM config, sending new parameters.");
536 write_u32le_inc(&wrptr, period);
537 write_u32le_inc(&wrptr, duty);
538 ret = ctrl_out(sdi, CMD_FPGA_SPI, reg_base, 0, buf, wrptr - buf);
540 sr_err("Cannot change PWM parameters.");
544 /* Enable configured channel after write completion. */
545 sr_spew("PWM config, enabling after param change.");
546 reg_val = enable_all | enable_cfg;
547 ret = ctrl_out(sdi, CMD_FPGA_SPI, REG_PWM_EN, 0,
548 ®_val, sizeof(reg_val));
550 sr_err("Cannot adjust PWM enabled state.");
558 * Determine the number of enabled channels as well as their bitmask
559 * representation. Derive data here which later simplifies processing
560 * of raw capture data memory content in streaming mode.
562 static void la2016_prepare_stream(const struct sr_dev_inst *sdi)
564 struct dev_context *devc;
565 struct stream_state_t *stream;
568 struct sr_channel *ch;
571 stream = &devc->stream;
572 memset(stream, 0, sizeof(*stream));
574 stream->enabled_count = 0;
575 for (l = sdi->channels; l; l = l->next) {
577 if (ch->type != SR_CHANNEL_LOGIC)
581 channel_mask = 1UL << ch->index;
582 stream->enabled_mask |= channel_mask;
583 stream->channel_masks[stream->enabled_count++] = channel_mask;
585 stream->channel_index = 0;
589 * This routine configures the set of enabled channels, as well as the
590 * trigger condition (if one was specified). Also prepares the capture
591 * data processing in stream mode, where the memory layout dramatically
592 * differs from normal mode.
594 static int set_trigger_config(const struct sr_dev_inst *sdi)
596 struct dev_context *devc;
597 struct sr_trigger *trigger;
599 uint32_t channels; /* Actually: Enabled channels? */
600 uint32_t enabled; /* Actually: Triggering channels? */
602 uint32_t high_or_falling;
606 struct sr_trigger_stage *stage1;
607 struct sr_trigger_match *match;
610 uint8_t buf[REG_UNKNOWN_30 - REG_TRIGGER]; /* Width of REG_TRIGGER. */
615 la2016_prepare_stream(sdi);
617 memset(&cfg, 0, sizeof(cfg));
618 cfg.channels = devc->stream.enabled_mask;
620 sr_err("Need at least one enabled logic channel.");
623 trigger = sr_session_trigger_get(sdi->session);
624 if (trigger && trigger->stages) {
625 stages = trigger->stages;
626 stage1 = stages->data;
628 sr_err("Only one trigger stage supported for now.");
631 channel = stage1->matches;
633 match = channel->data;
634 ch_mask = 1UL << match->channel->index;
636 switch (match->match) {
637 case SR_TRIGGER_ZERO:
638 cfg.level |= ch_mask;
639 cfg.high_or_falling &= ~ch_mask;
642 cfg.level |= ch_mask;
643 cfg.high_or_falling |= ch_mask;
645 case SR_TRIGGER_RISING:
646 if ((cfg.enabled & ~cfg.level)) {
647 sr_err("Device only supports one edge trigger.");
650 cfg.level &= ~ch_mask;
651 cfg.high_or_falling &= ~ch_mask;
653 case SR_TRIGGER_FALLING:
654 if ((cfg.enabled & ~cfg.level)) {
655 sr_err("Device only supports one edge trigger.");
658 cfg.level &= ~ch_mask;
659 cfg.high_or_falling |= ch_mask;
662 sr_err("Unknown trigger condition.");
665 cfg.enabled |= ch_mask;
666 channel = channel->next;
669 sr_dbg("Set trigger config: "
670 "enabled-channels 0x%04x, triggering-channels 0x%04x, "
671 "level-triggered 0x%04x, high/falling 0x%04x.",
672 cfg.channels, cfg.enabled, cfg.level, cfg.high_or_falling);
675 * Don't configure hardware trigger parameters in streaming mode
676 * or when the device lacks local memory. Yet the above dump of
677 * derived parameters from user specs is considered valueable.
679 * TODO Add support for soft triggers when hardware triggers in
680 * the device are not used or are not available at all.
682 if (!devc->model->memory_bits || devc->continuous) {
683 if (!devc->model->memory_bits)
684 sr_dbg("Device without memory. No hardware triggers.");
685 else if (devc->continuous)
686 sr_dbg("Streaming mode. No hardware triggers.");
689 cfg.high_or_falling = 0;
692 devc->trigger_involved = cfg.enabled != 0;
695 write_u32le_inc(&wrptr, cfg.channels);
696 write_u32le_inc(&wrptr, cfg.enabled);
697 write_u32le_inc(&wrptr, cfg.level);
698 write_u32le_inc(&wrptr, cfg.high_or_falling);
700 * Comment on this literal 16. Origin, meaning? Cannot be the
701 * register offset, nor the transfer length. Is it a channels
702 * count that is relevant for 16 and 32 channel models? Is it
703 * an obsolete experiment?
705 ret = ctrl_out(sdi, CMD_FPGA_SPI, REG_TRIGGER, 16, buf, wrptr - buf);
707 sr_err("Cannot setup trigger configuration.");
715 * This routine communicates the sample configuration to the device:
716 * Total samples count and samplerate, pre-trigger configuration.
718 static int set_sample_config(const struct sr_dev_inst *sdi)
720 struct dev_context *devc;
722 uint64_t min_samplerate, eff_samplerate;
723 uint64_t stream_bandwidth;
724 uint16_t divider_u16;
725 uint64_t limit_samples;
726 uint64_t pre_trigger_samples;
727 uint64_t pre_trigger_memory;
728 uint8_t buf[REG_TRIGGER - REG_SAMPLING]; /* Width of REG_SAMPLING. */
735 * The base clock need not be identical to the maximum samplerate,
736 * and differs between models. The 500MHz devices even use a base
737 * clock of 800MHz, and communicate divider 1 to the hardware to
738 * configure the 500MHz samplerate. This allows them to operate at
739 * a 200MHz samplerate which uses divider 4.
741 if (devc->samplerate > devc->model->samplerate) {
742 sr_err("Too high a sample rate: %" PRIu64 ".",
746 baseclock = devc->model->baseclock;
748 baseclock = devc->model->samplerate;
749 min_samplerate = baseclock;
750 min_samplerate /= 65536;
751 if (devc->samplerate < min_samplerate) {
752 sr_err("Too low a sample rate: %" PRIu64 ".",
756 divider_u16 = baseclock / devc->samplerate;
757 eff_samplerate = baseclock / divider_u16;
758 if (eff_samplerate > devc->model->samplerate)
759 eff_samplerate = devc->model->samplerate;
761 ret = sr_sw_limits_get_remain(&devc->sw_limits,
762 &limit_samples, NULL, NULL, NULL);
764 sr_err("Cannot get acquisition limits.");
767 if (limit_samples > LA2016_NUM_SAMPLES_MAX) {
768 sr_warn("Too high a sample depth: %" PRIu64 ", capping.",
770 limit_samples = LA2016_NUM_SAMPLES_MAX;
772 if (limit_samples == 0) {
773 limit_samples = LA2016_NUM_SAMPLES_MAX;
774 sr_dbg("Passing %" PRIu64 " to HW for unlimited samples.",
779 * The acquisition configuration communicates "pre-trigger"
780 * specs in several formats. sigrok users provide a percentage
781 * (0-100%), which translates to a pre-trigger samples count
782 * (assuming that a total samples count limit was specified).
783 * The device supports hardware compression, which depends on
784 * slowly changing input data to be effective. Fast changing
785 * input data may occupy more space in sample memory than its
786 * uncompressed form would. This is why a third parameter can
787 * limit the amount of sample memory to use for pre-trigger
788 * data. Only the upper 24 bits of that memory size spec get
789 * communicated to the device (written to its FPGA register).
791 if (!devc->model->memory_bits) {
792 sr_dbg("Memory-less device, skipping pre-trigger config.");
793 pre_trigger_samples = 0;
794 pre_trigger_memory = 0;
795 } else if (devc->trigger_involved) {
796 pre_trigger_samples = limit_samples;
797 pre_trigger_samples *= devc->capture_ratio;
798 pre_trigger_samples /= 100;
799 pre_trigger_memory = devc->model->memory_bits;
800 pre_trigger_memory *= UINT64_C(1024 * 1024 * 1024);
801 pre_trigger_memory /= 8; /* devc->model->channel_count ? */
802 pre_trigger_memory *= devc->capture_ratio;
803 pre_trigger_memory /= 100;
805 sr_dbg("No trigger setup, skipping pre-trigger config.");
806 pre_trigger_samples = 0;
807 pre_trigger_memory = 0;
809 /* Ensure non-zero value after LSB shift out in HW reg. */
810 if (pre_trigger_memory < 0x100)
811 pre_trigger_memory = 0x100;
813 sr_dbg("Set sample config: %" PRIu64 "kHz (div %" PRIu16 "), %" PRIu64 " samples.",
814 eff_samplerate / SR_KHZ(1), divider_u16, limit_samples);
815 sr_dbg("Capture ratio %" PRIu64 "%%, count %" PRIu64 ", mem %" PRIu64 ".",
816 devc->capture_ratio, pre_trigger_samples, pre_trigger_memory);
818 if (devc->continuous) {
819 stream_bandwidth = eff_samplerate;
820 stream_bandwidth *= devc->stream.enabled_count;
821 sr_dbg("Streaming: channel count %zu, product %" PRIu64 ".",
822 devc->stream.enabled_count, stream_bandwidth);
823 stream_bandwidth /= 1000 * 1000;
824 if (stream_bandwidth >= LA2016_STREAM_MBPS_MAX) {
825 sr_warn("High USB stream bandwidth: %" PRIu64 "Mbps.",
828 if (stream_bandwidth < LA2016_STREAM_PUSH_THR) {
829 sr_dbg("Streaming: low Mbps, suggest periodic flush.");
830 devc->stream.flush_period_ms = LA2016_STREAM_PUSH_IVAL;
835 * The acquisition configuration occupies a total of 16 bytes:
836 * - A 34bit total samples count limit (up to 10 billions) that
837 * is kept in a 40bit register.
838 * - A 34bit pre-trigger samples count limit (up to 10 billions)
839 * in another 40bit register.
840 * - A 32bit pre-trigger memory space limit (in bytes) of which
841 * the upper 24bits are kept in an FPGA register.
842 * - A 16bit clock divider which gets applied to the maximum
843 * samplerate of the device.
844 * - An 8bit register of unknown meaning. Currently always 0.
847 write_u40le_inc(&wrptr, limit_samples);
848 write_u40le_inc(&wrptr, pre_trigger_samples);
849 write_u24le_inc(&wrptr, pre_trigger_memory >> 8);
850 write_u16le_inc(&wrptr, divider_u16);
851 write_u8_inc(&wrptr, 0);
852 ret = ctrl_out(sdi, CMD_FPGA_SPI, REG_SAMPLING, 0, buf, wrptr - buf);
854 sr_err("Cannot setup acquisition configuration.");
862 * FPGA register REG_RUN holds the run state (u16le format). Bit fields
864 * bit 0: value 1 = idle
865 * bit 1: value 1 = writing to SDRAM
866 * bit 2: value 0 = waiting for trigger, 1 = trigger seen
867 * bit 3: value 0 = pretrigger sampling, 1 = posttrigger sampling
868 * The meaning of other bit fields is unknown.
870 * Typical values in order of appearance during execution:
871 * 0x85e1: idle, no acquisition pending
872 * IDLE set, TRGD don't care, POST don't care; DRAM don't care
873 * "In idle state." Takes precedence over all others.
874 * 0x85e2: pre-sampling, samples before the trigger position,
875 * when capture ratio > 0%
876 * IDLE clear, TRGD clear, POST clear; DRAM don't care
877 * "Not idle any more, no post yet, not triggered yet."
878 * 0x85ea: pre-sampling complete, now waiting for the trigger
879 * (whilst sampling continuously)
880 * IDLE clear, TRGD clear, POST set; DRAM don't care
881 * "Post set thus after pre, not triggered yet"
882 * 0x85ee: trigger seen, capturing post-trigger samples, running
883 * IDLE clear, TRGD set, POST set; DRAM don't care
884 * "Triggered and in post, not idle yet."
886 * IDLE set, TRGD don't care, POST don't care; DRAM don't care
887 * "In idle state." TRGD/POST don't care, same meaning as above.
889 static const uint16_t runstate_mask_idle = RUNSTATE_IDLE_BIT;
890 static const uint16_t runstate_patt_idle = RUNSTATE_IDLE_BIT;
891 static const uint16_t runstate_mask_step =
892 RUNSTATE_IDLE_BIT | RUNSTATE_TRGD_BIT | RUNSTATE_POST_BIT;
893 static const uint16_t runstate_patt_pre_trig = 0;
894 static const uint16_t runstate_patt_wait_trig = RUNSTATE_POST_BIT;
895 static const uint16_t runstate_patt_post_trig =
896 RUNSTATE_TRGD_BIT | RUNSTATE_POST_BIT;
898 static uint16_t run_state(const struct sr_dev_inst *sdi)
900 static uint16_t previous_state;
904 uint8_t buff[REG_PWM_EN - REG_RUN]; /* Width of REG_RUN. */
905 const uint8_t *rdptr;
908 ret = ctrl_in(sdi, CMD_FPGA_SPI, REG_RUN, 0, buff, sizeof(state));
910 sr_err("Cannot read run state.");
914 state = read_u16le_inc(&rdptr);
917 * Avoid flooding the log, only dump values as they change.
918 * The routine is called about every 50ms.
920 if (state == previous_state)
923 previous_state = state;
925 if ((state & runstate_mask_idle) == runstate_patt_idle)
927 if ((state & runstate_mask_step) == runstate_patt_pre_trig)
928 label = "pre-trigger sampling";
929 if ((state & runstate_mask_step) == runstate_patt_wait_trig)
930 label = "sampling, waiting for trigger";
931 if ((state & runstate_mask_step) == runstate_patt_post_trig)
932 label = "post-trigger sampling";
934 sr_dbg("Run state: 0x%04x (%s).", state, label);
936 sr_dbg("Run state: 0x%04x.", state);
941 static gboolean la2016_is_idle(const struct sr_dev_inst *sdi)
945 state = run_state(sdi);
946 if ((state & runstate_mask_idle) == runstate_patt_idle)
952 static int set_run_mode(const struct sr_dev_inst *sdi, uint8_t mode)
956 ret = ctrl_out(sdi, CMD_FPGA_SPI, REG_RUN, 0, &mode, sizeof(mode));
958 sr_err("Cannot configure run mode %d.", mode);
965 static int get_capture_info(const struct sr_dev_inst *sdi)
967 struct dev_context *devc;
969 uint8_t buf[REG_TRIGGER - REG_SAMPLING]; /* Width of REG_SAMPLING. */
970 const uint8_t *rdptr;
974 ret = ctrl_in(sdi, CMD_FPGA_SPI, REG_SAMPLING, 0, buf, sizeof(buf));
976 sr_err("Cannot read capture info.");
981 devc->info.n_rep_packets = read_u32le_inc(&rdptr);
982 devc->info.n_rep_packets_before_trigger = read_u32le_inc(&rdptr);
983 devc->info.write_pos = read_u32le_inc(&rdptr);
985 sr_dbg("Capture info: n_rep_packets: 0x%08x/%d, before_trigger: 0x%08x/%d, write_pos: 0x%08x/%d.",
986 devc->info.n_rep_packets, devc->info.n_rep_packets,
987 devc->info.n_rep_packets_before_trigger,
988 devc->info.n_rep_packets_before_trigger,
989 devc->info.write_pos, devc->info.write_pos);
991 if (devc->info.n_rep_packets % devc->packets_per_chunk) {
992 sr_warn("Unexpected packets count %lu, not a multiple of %lu.",
993 (unsigned long)devc->info.n_rep_packets,
994 (unsigned long)devc->packets_per_chunk);
1000 SR_PRIV int la2016_upload_firmware(const struct sr_dev_inst *sdi,
1001 struct sr_context *sr_ctx, libusb_device *dev, gboolean skip_upload)
1003 struct dev_context *devc;
1008 devc = sdi ? sdi->priv : NULL;
1009 if (!devc || !devc->usb_pid)
1011 pid = devc->usb_pid;
1013 fw = g_strdup_printf(MCU_FWFILE_FMT, pid);
1014 sr_info("USB PID %04hx, MCU firmware '%s'.", pid, fw);
1015 devc->mcu_firmware = g_strdup(fw);
1020 ret = ezusb_upload_firmware(sr_ctx, dev, USB_CONFIGURATION, fw);
1028 static void LIBUSB_CALL receive_transfer(struct libusb_transfer *xfer);
1030 static void la2016_usbxfer_release_cb(gpointer p)
1032 struct libusb_transfer *xfer;
1035 g_free(xfer->buffer);
1036 libusb_free_transfer(xfer);
1039 static int la2016_usbxfer_release(const struct sr_dev_inst *sdi)
1041 struct dev_context *devc;
1043 devc = sdi ? sdi->priv : NULL;
1047 /* Release all USB transfers. */
1048 g_slist_free_full(devc->transfers, la2016_usbxfer_release_cb);
1049 devc->transfers = NULL;
1054 static int la2016_usbxfer_allocate(const struct sr_dev_inst *sdi)
1056 struct dev_context *devc;
1057 size_t bufsize, xfercount;
1059 struct libusb_transfer *xfer;
1061 devc = sdi ? sdi->priv : NULL;
1065 /* Transfers were already allocated before? */
1066 if (devc->transfers)
1070 * Allocate all USB transfers and their buffers. Arrange for a
1071 * buffer size which is within the device's capabilities, and
1072 * is a multiple of the USB endpoint's size, to make use of the
1073 * RAW_IO performance feature.
1075 * Implementation detail: The LA2016_USB_BUFSZ value happens
1076 * to match all those constraints. No additional arithmetics is
1077 * required in this location.
1079 bufsize = LA2016_USB_BUFSZ;
1080 xfercount = LA2016_USB_XFER_COUNT;
1081 while (xfercount--) {
1082 buffer = g_try_malloc(bufsize);
1084 sr_err("Cannot allocate USB transfer buffer.");
1085 return SR_ERR_MALLOC;
1087 xfer = libusb_alloc_transfer(0);
1089 sr_err("Cannot allocate USB transfer.");
1091 return SR_ERR_MALLOC;
1093 xfer->buffer = buffer;
1094 devc->transfers = g_slist_append(devc->transfers, xfer);
1096 devc->transfer_bufsize = bufsize;
1101 static int la2016_usbxfer_cancel_all(const struct sr_dev_inst *sdi)
1103 struct dev_context *devc;
1105 struct libusb_transfer *xfer;
1107 devc = sdi ? sdi->priv : NULL;
1111 /* Unconditionally cancel the transfer. Ignore errors. */
1112 for (l = devc->transfers; l; l = l->next) {
1116 libusb_cancel_transfer(xfer);
1122 static int la2016_usbxfer_resubmit(const struct sr_dev_inst *sdi,
1123 struct libusb_transfer *xfer)
1125 struct dev_context *devc;
1126 struct sr_usb_dev_inst *usb;
1127 libusb_transfer_cb_fn cb;
1130 devc = sdi ? sdi->priv : NULL;
1131 usb = sdi ? sdi->conn : NULL;
1138 cb = receive_transfer;
1139 libusb_fill_bulk_transfer(xfer, usb->devhdl,
1140 USB_EP_CAPTURE_DATA | LIBUSB_ENDPOINT_IN,
1141 xfer->buffer, devc->transfer_bufsize,
1142 cb, (void *)sdi, CAPTURE_TIMEOUT_MS);
1143 ret = libusb_submit_transfer(xfer);
1145 sr_err("Cannot submit USB transfer: %s.",
1146 libusb_error_name(ret));
1153 static int la2016_usbxfer_submit_all(const struct sr_dev_inst *sdi)
1155 struct dev_context *devc;
1157 struct libusb_transfer *xfer;
1160 devc = sdi ? sdi->priv : NULL;
1164 for (l = devc->transfers; l; l = l->next) {
1168 ret = la2016_usbxfer_resubmit(sdi, xfer);
1176 SR_PRIV int la2016_setup_acquisition(const struct sr_dev_inst *sdi,
1179 struct dev_context *devc;
1185 ret = set_threshold_voltage(sdi, voltage);
1189 cmd = devc->continuous ? CAPTMODE_STREAM : CAPTMODE_TO_RAM;
1190 ret = ctrl_out(sdi, CMD_FPGA_SPI, REG_CAPT_MODE, 0, &cmd, sizeof(cmd));
1192 sr_err("Cannot send command to stop sampling.");
1196 ret = set_trigger_config(sdi);
1200 ret = set_sample_config(sdi);
1207 SR_PRIV int la2016_start_acquisition(const struct sr_dev_inst *sdi)
1209 struct dev_context *devc;
1214 ret = la2016_usbxfer_allocate(sdi);
1218 if (devc->continuous) {
1219 ret = ctrl_out(sdi, CMD_BULK_RESET, 0x00, 0, NULL, 0);
1223 ret = la2016_usbxfer_submit_all(sdi);
1228 * Periodic receive callback will set runmode. This
1229 * activity MUST be close to data reception, a pause
1230 * between these steps breaks the stream's operation.
1233 ret = set_run_mode(sdi, RUNMODE_RUN);
1241 static int la2016_stop_acquisition(const struct sr_dev_inst *sdi)
1243 struct dev_context *devc;
1246 ret = set_run_mode(sdi, RUNMODE_HALT);
1251 if (devc->continuous)
1252 devc->download_finished = TRUE;
1257 SR_PRIV int la2016_abort_acquisition(const struct sr_dev_inst *sdi)
1261 ret = la2016_stop_acquisition(sdi);
1265 (void)la2016_usbxfer_cancel_all(sdi);
1270 static int la2016_start_download(const struct sr_dev_inst *sdi)
1272 struct dev_context *devc;
1274 uint8_t wrbuf[REG_SAMPLING - REG_BULK]; /* Width of REG_BULK. */
1279 ret = get_capture_info(sdi);
1283 devc->n_transfer_packets_to_read = devc->info.n_rep_packets;
1284 devc->n_transfer_packets_to_read /= devc->packets_per_chunk;
1285 devc->n_bytes_to_read = devc->n_transfer_packets_to_read;
1286 devc->n_bytes_to_read *= TRANSFER_PACKET_LENGTH;
1287 devc->read_pos = devc->info.write_pos - devc->n_bytes_to_read;
1288 devc->n_reps_until_trigger = devc->info.n_rep_packets_before_trigger;
1290 sr_dbg("Want to read %u xfer-packets starting from pos %" PRIu32 ".",
1291 devc->n_transfer_packets_to_read, devc->read_pos);
1293 ret = ctrl_out(sdi, CMD_BULK_RESET, 0x00, 0, NULL, 0);
1295 sr_err("Cannot reset USB bulk state.");
1298 sr_dbg("Will read from 0x%08lx, 0x%08x bytes.",
1299 (unsigned long)devc->read_pos, devc->n_bytes_to_read);
1301 write_u32le_inc(&wrptr, devc->read_pos);
1302 write_u32le_inc(&wrptr, devc->n_bytes_to_read);
1303 ret = ctrl_out(sdi, CMD_FPGA_SPI, REG_BULK, 0, wrbuf, wrptr - wrbuf);
1305 sr_err("Cannot send USB bulk config.");
1309 ret = la2016_usbxfer_submit_all(sdi);
1311 sr_err("Cannot submit USB bulk transfers.");
1315 ret = ctrl_out(sdi, CMD_BULK_START, 0x00, 0, NULL, 0);
1317 sr_err("Cannot start USB bulk transfers.");
1325 * A chunk (received via USB) contains a number of transfers (USB length
1326 * divided by 16) which contain a number of packets (5 per transfer) which
1327 * contain a number of samples (8bit repeat count per 16bit sample data).
1329 static void send_chunk(struct sr_dev_inst *sdi,
1330 const uint8_t *data_buffer, size_t data_length)
1332 struct dev_context *devc;
1333 size_t num_xfers, num_pkts;
1335 uint32_t sample_value;
1337 uint8_t sample_buff[sizeof(sample_value)];
1341 /* Ignore incoming USB data after complete sample data download. */
1342 if (devc->download_finished)
1345 if (devc->trigger_involved && !devc->trigger_marked && devc->info.n_rep_packets_before_trigger == 0) {
1346 feed_queue_logic_send_trigger(devc->feed_queue);
1347 devc->trigger_marked = TRUE;
1351 * Adjust the number of remaining bytes to read from the device
1352 * before the processing of the currently received chunk affects
1353 * the variable which holds the number of received bytes.
1355 if (data_length > devc->n_bytes_to_read)
1356 devc->n_bytes_to_read = 0;
1358 devc->n_bytes_to_read -= data_length;
1360 /* Process the received chunk of capture data. */
1363 num_xfers = data_length / TRANSFER_PACKET_LENGTH;
1364 while (num_xfers--) {
1365 num_pkts = devc->packets_per_chunk;
1366 while (num_pkts--) {
1368 /* TODO Verify 32channel layout. */
1369 if (devc->model->channel_count == 32)
1370 sample_value = read_u32le_inc(&rp);
1371 else if (devc->model->channel_count == 16)
1372 sample_value = read_u16le_inc(&rp);
1373 repetitions = read_u8_inc(&rp);
1375 devc->total_samples += repetitions;
1377 write_u32le(sample_buff, sample_value);
1378 feed_queue_logic_submit(devc->feed_queue,
1379 sample_buff, repetitions);
1380 sr_sw_limits_update_samples_read(&devc->sw_limits,
1383 if (devc->trigger_involved && !devc->trigger_marked) {
1384 if (!--devc->n_reps_until_trigger) {
1385 feed_queue_logic_send_trigger(devc->feed_queue);
1386 devc->trigger_marked = TRUE;
1387 sr_dbg("Trigger position after %" PRIu64 " samples, %.6fms.",
1388 devc->total_samples,
1389 (double)devc->total_samples / devc->samplerate * 1e3);
1393 (void)read_u8_inc(&rp); /* Skip sequence number. */
1397 * Check for several conditions which shall terminate the
1398 * capture data download: When the amount of capture data in
1399 * the device is exhausted. When the user specified samples
1400 * count limit is reached.
1402 if (!devc->n_bytes_to_read) {
1403 devc->download_finished = TRUE;
1405 sr_dbg("%" PRIu32 " more bytes to download from the device.",
1406 devc->n_bytes_to_read);
1408 if (!devc->download_finished && sr_sw_limits_check(&devc->sw_limits)) {
1409 sr_dbg("Acquisition limit reached.");
1410 devc->download_finished = TRUE;
1412 if (devc->download_finished) {
1413 sr_dbg("Download finished, flushing session feed queue.");
1414 feed_queue_logic_flush(devc->feed_queue);
1416 sr_dbg("Total samples after chunk: %" PRIu64 ".", devc->total_samples);
1420 * Process a chunk of capture data in streaming mode. The memory layout
1421 * is rather different from "normal mode" (see the send_chunk() routine
1422 * above). In streaming mode data is not compressed, and memory cells
1423 * neither contain raw sampled pin values at a given point in time. The
1424 * memory content needs transformation.
1425 * - The memory content can be seen as a sequence of memory cells.
1426 * - Each cell contains samples that correspond to the same channel.
1427 * The next cell contains samples for the next channel, etc.
1428 * - Only enabled channels occupy memory cells. Disabled channels are
1429 * not part of the capture data memory layout.
1430 * - The LSB bit position in a cell is the sample which was taken first
1431 * for this channel. Upper bit positions were taken later.
1433 * Implementor's note: This routine is inspired by convert_sample_data()
1434 * in the https://github.com/AlexUg/sigrok implementation. Which in turn
1435 * appears to have been derived from the saleae-logic16 sigrok driver.
1436 * The code is phrased conservatively to verify the layout as discussed
1437 * above, performance was not a priority. Operation was verified with an
1438 * LA2016 device. The memory layout of 32 channel models is yet to get
1441 static void stream_data(struct sr_dev_inst *sdi,
1442 const uint8_t *data_buffer, size_t data_length)
1444 struct dev_context *devc;
1445 struct stream_state_t *stream;
1448 uint32_t sample_value;
1449 uint8_t sample_buff[sizeof(sample_value)];
1454 stream = &devc->stream;
1456 /* Ignore incoming USB data after complete sample data download. */
1457 if (devc->download_finished)
1459 sr_dbg("Stream mode, got another chunk: %p, length %zu.",
1460 data_buffer, data_length);
1462 /* TODO Add soft trigger support when in stream mode? */
1465 * TODO Are memory cells always as wide as the channel count?
1466 * Are they always 16bits wide? Verify for 32 channel devices.
1468 bit_count = devc->model->channel_count;
1469 if (bit_count == 32) {
1470 data_length /= sizeof(uint32_t);
1471 } else if (bit_count == 16) {
1472 data_length /= sizeof(uint16_t);
1475 * Unhandled case. Acquisition should not start.
1476 * The statement silences the compiler.
1482 while (data_length--) {
1483 /* Get another entity. */
1484 if (bit_count == 32)
1485 sample_value = read_u32le_inc(&rp);
1486 else if (bit_count == 16)
1487 sample_value = read_u16le_inc(&rp);
1489 /* Map the entity's bits to a channel's samples. */
1490 ch_mask = stream->channel_masks[stream->channel_index];
1491 for (bit_idx = 0; bit_idx < bit_count; bit_idx++) {
1492 if (sample_value & (1UL << bit_idx))
1493 stream->sample_data[bit_idx] |= ch_mask;
1497 * Advance to the next channel. Submit a block of
1498 * samples when all channels' data was seen.
1500 stream->channel_index++;
1501 if (stream->channel_index != stream->enabled_count)
1503 for (bit_idx = 0; bit_idx < bit_count; bit_idx++) {
1504 sample_value = stream->sample_data[bit_idx];
1505 write_u32le(sample_buff, sample_value);
1506 feed_queue_logic_submit(devc->feed_queue, sample_buff, 1);
1508 sr_sw_limits_update_samples_read(&devc->sw_limits, bit_count);
1509 devc->total_samples += bit_count;
1510 memset(stream->sample_data, 0, sizeof(stream->sample_data));
1511 stream->channel_index = 0;
1515 * Need we count empty or failed USB transfers? This version
1516 * doesn't, assumes that timeouts are perfectly legal because
1517 * transfers are started early, and slow samplerates or trigger
1518 * support in hardware are plausible causes for empty transfers.
1520 * TODO Maybe a good condition would be (rather large) a timeout
1521 * after a previous capture data chunk was seen? So that stalled
1522 * streaming gets detected which _is_ an exceptional condition.
1523 * We have observed these when "runmode" is set early but bulk
1524 * transfers start late with a pause after setting the runmode.
1526 if (sr_sw_limits_check(&devc->sw_limits)) {
1527 sr_dbg("Acquisition end reached (sw limits).");
1528 devc->download_finished = TRUE;
1530 if (devc->download_finished) {
1531 sr_dbg("Stream receive done, flushing session feed queue.");
1532 feed_queue_logic_flush(devc->feed_queue);
1534 sr_dbg("Total samples after chunk: %" PRIu64 ".", devc->total_samples);
1537 static void LIBUSB_CALL receive_transfer(struct libusb_transfer *transfer)
1539 struct sr_dev_inst *sdi;
1540 struct dev_context *devc;
1541 gboolean was_cancelled, device_gone;
1544 sdi = transfer->user_data;
1547 was_cancelled = transfer->status == LIBUSB_TRANSFER_CANCELLED;
1548 device_gone = transfer->status == LIBUSB_TRANSFER_NO_DEVICE;
1549 sr_dbg("receive_transfer(): status %s received %d bytes.",
1550 libusb_error_name(transfer->status), transfer->actual_length);
1552 sr_warn("Lost communication to USB device.");
1553 devc->download_finished = TRUE;
1558 * Implementation detail: A USB transfer timeout is not fatal
1559 * here. We just process whatever was received, empty input is
1560 * perfectly acceptable. Reaching (or exceeding) the sw limits
1561 * or exhausting the device's captured data will complete the
1562 * sample data download.
1564 if (devc->continuous)
1565 stream_data(sdi, transfer->buffer, transfer->actual_length);
1567 send_chunk(sdi, transfer->buffer, transfer->actual_length);
1570 * Re-submit completed transfers (regardless of timeout or
1571 * data reception), unless the transfer was cancelled when
1572 * the acquisition was terminated or has completed.
1574 if (!was_cancelled && !devc->download_finished) {
1575 ret = la2016_usbxfer_resubmit(sdi, transfer);
1578 devc->download_finished = TRUE;
1582 SR_PRIV int la2016_receive_data(int fd, int revents, void *cb_data)
1584 const struct sr_dev_inst *sdi;
1585 struct dev_context *devc;
1586 struct drv_context *drvc;
1595 drvc = sdi->driver->context;
1597 /* Arrange for the start of stream mode when requested. */
1598 if (devc->continuous && !devc->frame_begin_sent) {
1599 sr_dbg("First receive callback in stream mode.");
1600 devc->download_finished = FALSE;
1601 devc->trigger_marked = FALSE;
1602 devc->total_samples = 0;
1604 std_session_send_df_frame_begin(sdi);
1605 devc->frame_begin_sent = TRUE;
1607 ret = set_run_mode(sdi, RUNMODE_RUN);
1609 sr_err("Cannot set 'runmode' to 'run'.");
1613 ret = ctrl_out(sdi, CMD_BULK_START, 0x00, 0, NULL, 0);
1615 sr_err("Cannot start USB bulk transfers.");
1618 sr_dbg("Stream data reception initiated.");
1622 * Wait for the acquisition to complete in hardware.
1623 * Periodically check a potentially configured msecs timeout.
1625 if (!devc->continuous && !devc->completion_seen) {
1626 if (!la2016_is_idle(sdi)) {
1627 if (sr_sw_limits_check(&devc->sw_limits)) {
1628 devc->sw_limits.limit_msec = 0;
1629 sr_dbg("Limit reached. Stopping acquisition.");
1630 la2016_stop_acquisition(sdi);
1632 /* Not yet ready for sample data download. */
1635 sr_dbg("Acquisition completion seen (hardware).");
1636 devc->sw_limits.limit_msec = 0;
1637 devc->completion_seen = TRUE;
1638 devc->download_finished = FALSE;
1639 devc->trigger_marked = FALSE;
1640 devc->total_samples = 0;
1642 la2016_dump_fpga_registers(sdi, "acquisition complete", 0, 0);
1644 /* Initiate the download of acquired sample data. */
1645 std_session_send_df_frame_begin(sdi);
1646 devc->frame_begin_sent = TRUE;
1647 ret = la2016_start_download(sdi);
1649 sr_err("Cannot start acquisition data download.");
1652 sr_dbg("Acquisition data download started.");
1657 /* Handle USB reception. Drives sample data download. */
1658 memset(&tv, 0, sizeof(tv));
1659 libusb_handle_events_timeout(drvc->sr_ctx->libusb_ctx, &tv);
1662 * Periodically flush acquisition data in streaming mode.
1663 * Without this nudge, previously received and accumulated data
1664 * keeps sitting in queues and is not seen by applications.
1666 if (devc->continuous && devc->stream.flush_period_ms) {
1667 uint64_t now, elapsed;
1668 now = g_get_monotonic_time();
1669 if (!devc->stream.last_flushed)
1670 devc->stream.last_flushed = now;
1671 elapsed = now - devc->stream.last_flushed;
1673 if (elapsed >= devc->stream.flush_period_ms) {
1674 sr_dbg("Stream mode, flushing.");
1675 feed_queue_logic_flush(devc->feed_queue);
1676 devc->stream.last_flushed = now;
1680 /* Postprocess completion of sample data download. */
1681 if (devc->download_finished) {
1682 sr_dbg("Download finished, post processing.");
1684 la2016_stop_acquisition(sdi);
1685 usb_source_remove(sdi->session, drvc->sr_ctx);
1687 la2016_usbxfer_cancel_all(sdi);
1688 memset(&tv, 0, sizeof(tv));
1689 libusb_handle_events_timeout(drvc->sr_ctx->libusb_ctx, &tv);
1691 feed_queue_logic_flush(devc->feed_queue);
1692 feed_queue_logic_free(devc->feed_queue);
1693 devc->feed_queue = NULL;
1694 if (devc->frame_begin_sent) {
1695 std_session_send_df_frame_end(sdi);
1696 devc->frame_begin_sent = FALSE;
1698 std_session_send_df_end(sdi);
1700 sr_dbg("Download finished, done post processing.");
1706 SR_PRIV int la2016_identify_device(const struct sr_dev_inst *sdi,
1707 gboolean show_message)
1709 struct dev_context *devc;
1710 uint8_t buf[8]; /* Larger size of manuf date and device type magic. */
1711 size_t rdoff, rdlen;
1712 const uint8_t *rdptr;
1713 uint8_t date_yy, date_mm;
1714 uint8_t dinv_yy, dinv_mm;
1715 uint8_t magic, magic2;
1717 const struct kingst_model *model;
1723 * Four EEPROM bytes at offset 0x20 are the manufacturing date,
1724 * year and month in BCD format, followed by inverted values for
1725 * consistency checks. For example bytes 20 04 df fb translate
1726 * to 2020-04. This information can help identify the vintage of
1727 * devices when unknown magic numbers are seen.
1730 rdlen = 4 * sizeof(uint8_t);
1731 ret = ctrl_in(sdi, CMD_EEPROM, rdoff, 0, buf, rdlen);
1732 if (ret != SR_OK && !show_message) {
1733 /* Non-fatal weak attempt during probe. Not worth logging. */
1734 sr_dbg("Cannot access EEPROM.");
1736 } else if (ret != SR_OK) {
1737 /* Failed attempt in regular use. Non-fatal. Worth logging. */
1738 sr_err("Cannot read manufacture date in EEPROM.");
1740 if (sr_log_loglevel_get() >= SR_LOG_SPEW) {
1742 txt = sr_hexdump_new(buf, rdlen);
1743 sr_spew("Manufacture date bytes %s.", txt->str);
1744 sr_hexdump_free(txt);
1747 date_yy = read_u8_inc(&rdptr);
1748 date_mm = read_u8_inc(&rdptr);
1749 dinv_yy = read_u8_inc(&rdptr);
1750 dinv_mm = read_u8_inc(&rdptr);
1751 sr_info("Manufacture date: 20%02hx-%02hx.", date_yy, date_mm);
1752 if ((date_mm ^ dinv_mm) != 0xff || (date_yy ^ dinv_yy) != 0xff)
1753 sr_warn("Manufacture date fails checksum test.");
1757 * Several Kingst logic analyzer devices share the same USB VID
1758 * and PID. The product ID determines which MCU firmware to load.
1759 * The MCU firmware provides access to EEPROM content which then
1760 * allows to identify the device model. Which in turn determines
1761 * which FPGA bitstream to load. Eight bytes at offset 0x08 are
1764 * EEPROM content for model identification is kept redundantly
1765 * in memory. The values are stored in verbatim and in inverted
1766 * form, multiple copies are kept at different offsets. Example
1777 * Exclusively inspecting the magic byte appears to be sufficient,
1778 * other fields seem to be 'don't care'.
1780 * magic 2 == LA2016 using "kingst-la2016-fpga.bitstream"
1781 * magic 3 == LA1016 using "kingst-la1016-fpga.bitstream"
1782 * magic 8 == LA2016a using "kingst-la2016a1-fpga.bitstream"
1783 * (latest v1.3.0 PCB, perhaps others)
1784 * magic 9 == LA1016a using "kingst-la1016a1-fpga.bitstream"
1785 * (latest v1.3.0 PCB, perhaps others)
1787 * When EEPROM content does not match the hardware configuration
1788 * (the board layout), the software may load but yield incorrect
1789 * results (like swapped channels). The FPGA bitstream itself
1790 * will authenticate with IC U10 and fail when its capabilities
1791 * do not match the hardware model. An LA1016 won't become a
1792 * LA2016 by faking its EEPROM content.
1794 devc->identify_magic = 0;
1796 rdlen = 8 * sizeof(uint8_t);
1797 ret = ctrl_in(sdi, CMD_EEPROM, rdoff, 0, &buf, rdlen);
1799 sr_err("Cannot read EEPROM device identifier bytes.");
1802 if (sr_log_loglevel_get() >= SR_LOG_SPEW) {
1804 txt = sr_hexdump_new(buf, rdlen);
1805 sr_spew("EEPROM magic bytes %s.", txt->str);
1806 sr_hexdump_free(txt);
1810 if ((buf[0] ^ buf[1]) == 0xff && (buf[2] ^ buf[3]) == 0xff) {
1811 /* Primary copy of magic passes complement check (4 bytes). */
1814 sr_dbg("Using primary magic 0x%hhx (0x%hhx).", magic, magic2);
1815 } else if ((buf[4] ^ buf[5]) == 0xff && (buf[6] ^ buf[7]) == 0xff) {
1816 /* Backup copy of magic passes complement check (4 bytes). */
1819 sr_dbg("Using secondary magic 0x%hhx (0x%hhx).", magic, magic2);
1820 } else if ((buf[0] ^ buf[1]) == 0xff) {
1821 /* Primary copy of magic passes complement check (2 bytes). */
1823 sr_dbg("Using primary magic 0x%hhx.", magic);
1824 } else if ((buf[4] ^ buf[5]) == 0xff) {
1825 /* Backup copy of magic passes complement check (2 bytes). */
1827 sr_dbg("Using secondary magic 0x%hhx.", magic);
1829 sr_err("Cannot find consistent device type identification.");
1831 devc->identify_magic = magic;
1832 devc->identify_magic2 = magic2;
1835 for (model_idx = 0; model_idx < ARRAY_SIZE(models); model_idx++) {
1836 model = &models[model_idx];
1837 if (model->magic != magic)
1839 if (model->magic2 && model->magic2 != magic2)
1841 devc->model = model;
1842 sr_info("Model '%s', %zu channels, max %" PRIu64 "MHz.",
1843 model->name, model->channel_count,
1844 model->samplerate / SR_MHZ(1));
1845 devc->fpga_bitstream = g_strdup_printf(FPGA_FWFILE_FMT,
1847 sr_info("FPGA bitstream file '%s'.", devc->fpga_bitstream);
1848 if (!model->channel_count) {
1849 sr_warn("Device lacks logic channels. Not supported.");
1855 sr_err("Cannot identify as one of the supported models.");
1862 SR_PRIV int la2016_init_hardware(const struct sr_dev_inst *sdi)
1864 struct dev_context *devc;
1865 const char *bitstream_fn;
1870 bitstream_fn = devc ? devc->fpga_bitstream : "";
1872 ret = check_fpga_bitstream(sdi);
1874 ret = upload_fpga_bitstream(sdi, bitstream_fn);
1876 sr_err("Cannot upload FPGA bitstream.");
1880 ret = enable_fpga_bitstream(sdi);
1882 sr_err("Cannot enable FPGA bitstream after upload.");
1886 state = run_state(sdi);
1887 if ((state & 0xfff0) != 0x85e0) {
1888 sr_warn("Unexpected run state, want 0x85eX, got 0x%04x.", state);
1891 ret = ctrl_out(sdi, CMD_BULK_RESET, 0x00, 0, NULL, 0);
1893 sr_err("Cannot reset USB bulk transfer.");
1897 sr_dbg("Device should be initialized.");
1902 SR_PRIV int la2016_deinit_hardware(const struct sr_dev_inst *sdi)
1906 ret = ctrl_out(sdi, CMD_FPGA_ENABLE, 0x00, 0, NULL, 0);
1908 sr_err("Cannot deinitialize device's FPGA.");
1915 SR_PRIV void la2016_release_resources(const struct sr_dev_inst *sdi)
1917 (void)la2016_usbxfer_release(sdi);
1920 SR_PRIV int la2016_write_pwm_config(const struct sr_dev_inst *sdi, size_t idx)
1922 return set_pwm_config(sdi, idx);