2 * This file is part of the libsigrok project.
4 * Copyright (C) 2013 Bert Vermeulen <bert@biot.com>
5 * Copyright (C) 2012 Joel Holdsworth <joel@airwebreathe.org.uk>
7 * This program is free software: you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation, either version 3 of the License, or
10 * (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program. If not, see <http://www.gnu.org/licenses/>.
21 #ifndef LIBSIGROK_HARDWARE_FX2LAFW_DSLOGIC_H
22 #define LIBSIGROK_HARDWARE_FX2LAFW_DSLOGIC_H
24 /* Modified protocol commands & flags used by DSLogic */
25 #define DS_CMD_GET_FW_VERSION 0xb0
26 #define DS_CMD_GET_REVID_VERSION 0xb1
27 #define DS_CMD_START 0xb2
28 #define DS_CMD_FPGA_FW 0xb3
29 #define DS_CMD_CONFIG 0xb4
31 #define DS_NUM_TRIGGER_STAGES 16
32 #define DS_START_FLAGS_STOP (1 << 7)
33 #define DS_START_FLAGS_CLK_48MHZ (1 << 6)
34 #define DS_START_FLAGS_SAMPLE_WIDE (1 << 5)
36 enum dslogic_operation_modes {
43 struct dslogic_version {
50 uint8_t sample_delay_h;
51 uint8_t sample_delay_l;
54 struct dslogic_trigger_pos {
57 uint8_t first_block[504];
61 * The FPGA is configured with TLV tuples. Length is specified as the
62 * number of 16-bit words, and the (type, length) header is in some
63 * cases padded with 0xffff.
65 #define _DS_CFG(variable, wordcnt) ((variable << 8) | wordcnt)
66 #define _DS_CFG_PAD(variable, wordcnt) ((_DS_CFG(variable, wordcnt) << 16) | 0xffff)
67 #define DS_CFG_START 0xffffffff
68 #define DS_CFG_MODE _DS_CFG(0, 1)
69 #define DS_CFG_DIVIDER _DS_CFG_PAD(1, 2)
70 #define DS_CFG_COUNT _DS_CFG_PAD(3, 2)
71 #define DS_CFG_TRIG_POS _DS_CFG_PAD(5, 2)
72 #define DS_CFG_TRIG_GLB _DS_CFG(7, 1)
73 #define DS_CFG_TRIG_ADP _DS_CFG_PAD(10, 2)
74 #define DS_CFG_TRIG_SDA _DS_CFG_PAD(12, 2)
75 #define DS_CFG_TRIG_MASK0 _DS_CFG_PAD(16, 16)
76 #define DS_CFG_TRIG_MASK1 _DS_CFG_PAD(17, 16)
77 #define DS_CFG_TRIG_VALUE0 _DS_CFG_PAD(20, 16)
78 #define DS_CFG_TRIG_VALUE1 _DS_CFG_PAD(21, 16)
79 #define DS_CFG_TRIG_EDGE0 _DS_CFG_PAD(24, 16)
80 #define DS_CFG_TRIG_EDGE1 _DS_CFG_PAD(25, 16)
81 #define DS_CFG_TRIG_COUNT0 _DS_CFG_PAD(28, 16)
82 #define DS_CFG_TRIG_COUNT1 _DS_CFG_PAD(29, 16)
83 #define DS_CFG_TRIG_LOGIC0 _DS_CFG_PAD(32, 16)
84 #define DS_CFG_TRIG_LOGIC1 _DS_CFG_PAD(33, 16)
85 #define DS_CFG_END 0x00000000
87 struct dslogic_fpga_config {
91 uint32_t divider_header;
93 uint32_t count_header;
95 uint32_t trig_pos_header;
97 uint16_t trig_glb_header;
99 uint32_t trig_adp_header;
101 uint32_t trig_sda_header;
103 uint32_t trig_mask0_header;
104 uint16_t trig_mask0[DS_NUM_TRIGGER_STAGES];
105 uint32_t trig_mask1_header;
106 uint16_t trig_mask1[DS_NUM_TRIGGER_STAGES];
107 uint32_t trig_value0_header;
108 uint16_t trig_value0[DS_NUM_TRIGGER_STAGES];
109 uint32_t trig_value1_header;
110 uint16_t trig_value1[DS_NUM_TRIGGER_STAGES];
111 uint32_t trig_edge0_header;
112 uint16_t trig_edge0[DS_NUM_TRIGGER_STAGES];
113 uint32_t trig_edge1_header;
114 uint16_t trig_edge1[DS_NUM_TRIGGER_STAGES];
115 uint32_t trig_count0_header;
116 uint16_t trig_count0[DS_NUM_TRIGGER_STAGES];
117 uint32_t trig_count1_header;
118 uint16_t trig_count1[DS_NUM_TRIGGER_STAGES];
119 uint32_t trig_logic0_header;
120 uint16_t trig_logic0[DS_NUM_TRIGGER_STAGES];
121 uint32_t trig_logic1_header;
122 uint16_t trig_logic1[DS_NUM_TRIGGER_STAGES];
126 SR_PRIV int dslogic_fpga_firmware_upload(const struct sr_dev_inst *sdi,
128 SR_PRIV int dslogic_start_acquisition(const struct sr_dev_inst *sdi);
129 SR_PRIV int dslogic_stop_acquisition(const struct sr_dev_inst *sdi);
130 SR_PRIV int dslogic_fpga_configure(const struct sr_dev_inst *sdi);