2 * This file is part of the libsigrok project.
4 * Copyright (C) 2013 Bert Vermeulen <bert@biot.com>
5 * Copyright (C) 2012 Joel Holdsworth <joel@airwebreathe.org.uk>
7 * This program is free software: you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation, either version 3 of the License, or
10 * (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program. If not, see <http://www.gnu.org/licenses/>.
24 #include <glib/gstdio.h>
28 #define FW_BUFSIZE (4 * 1024)
30 #define FPGA_UPLOAD_DELAY (10 * 1000)
32 #define USB_TIMEOUT (3 * 1000)
34 SR_PRIV int dslogic_fpga_firmware_upload(const struct sr_dev_inst *sdi,
38 struct sr_resource bitstream;
39 struct drv_context *drvc;
40 struct sr_usb_dev_inst *usb;
47 drvc = sdi->driver->context;
50 sr_dbg("Uploading FPGA firmware '%s'.", name);
52 result = sr_resource_open(drvc->sr_ctx, &bitstream,
53 SR_RESOURCE_FIRMWARE, name);
57 /* Tell the device firmware is coming. */
58 memset(cmd, 0, sizeof(cmd));
59 if ((ret = libusb_control_transfer(usb->devhdl, LIBUSB_REQUEST_TYPE_VENDOR |
60 LIBUSB_ENDPOINT_OUT, DS_CMD_FPGA_FW, 0x0000, 0x0000,
61 (unsigned char *)&cmd, sizeof(cmd), USB_TIMEOUT)) < 0) {
62 sr_err("Failed to upload FPGA firmware: %s.", libusb_error_name(ret));
63 sr_resource_close(drvc->sr_ctx, &bitstream);
67 /* Give the FX2 time to get ready for FPGA firmware upload. */
68 g_usleep(FPGA_UPLOAD_DELAY);
70 buf = g_malloc(FW_BUFSIZE);
74 chunksize = sr_resource_read(drvc->sr_ctx, &bitstream,
81 if ((ret = libusb_bulk_transfer(usb->devhdl, 2 | LIBUSB_ENDPOINT_OUT,
82 buf, chunksize, &transferred, USB_TIMEOUT)) < 0) {
83 sr_err("Unable to configure FPGA firmware: %s.",
84 libusb_error_name(ret));
89 sr_spew("Uploaded %" PRIu64 "/%" PRIu64 " bytes.",
92 if (transferred != chunksize) {
93 sr_err("Short transfer while uploading FPGA firmware.");
99 sr_resource_close(drvc->sr_ctx, &bitstream);
102 sr_dbg("FPGA firmware upload done.");
107 SR_PRIV int dslogic_start_acquisition(const struct sr_dev_inst *sdi)
109 struct dev_context *devc;
110 struct sr_usb_dev_inst *usb;
111 struct dslogic_mode mode;
116 mode.sample_delay_h = mode.sample_delay_l = 0;
117 if (devc->sample_wide)
118 mode.flags |= DS_START_FLAGS_SAMPLE_WIDE;
121 ret = libusb_control_transfer(usb->devhdl, LIBUSB_REQUEST_TYPE_VENDOR |
122 LIBUSB_ENDPOINT_OUT, DS_CMD_START, 0x0000, 0x0000,
123 (unsigned char *)&mode, sizeof(mode), USB_TIMEOUT);
125 sr_err("Failed to send start command: %s.", libusb_error_name(ret));
132 SR_PRIV int dslogic_stop_acquisition(const struct sr_dev_inst *sdi)
134 struct sr_usb_dev_inst *usb;
135 struct dslogic_mode mode;
138 mode.flags = DS_START_FLAGS_STOP;
139 mode.sample_delay_h = mode.sample_delay_l = 0;
142 ret = libusb_control_transfer(usb->devhdl, LIBUSB_REQUEST_TYPE_VENDOR |
143 LIBUSB_ENDPOINT_OUT, DS_CMD_START, 0x0000, 0x0000,
144 (unsigned char *)&mode, sizeof(struct dslogic_mode), USB_TIMEOUT);
146 sr_err("Failed to send stop command: %s.", libusb_error_name(ret));
153 SR_PRIV int dslogic_fpga_configure(const struct sr_dev_inst *sdi)
155 struct dev_context *devc;
156 struct sr_usb_dev_inst *usb;
158 struct dslogic_fpga_config cfg;
161 int transferred, len, ret;
163 sr_dbg("Configuring FPGA.");
167 WL32(&cfg.sync, DS_CFG_START);
168 WL16(&cfg.mode_header, DS_CFG_MODE);
169 WL32(&cfg.divider_header, DS_CFG_DIVIDER);
170 WL32(&cfg.count_header, DS_CFG_COUNT);
171 WL32(&cfg.trig_pos_header, DS_CFG_TRIG_POS);
172 WL16(&cfg.trig_glb_header, DS_CFG_TRIG_GLB);
173 WL32(&cfg.trig_adp_header, DS_CFG_TRIG_ADP);
174 WL32(&cfg.trig_sda_header, DS_CFG_TRIG_SDA);
175 WL32(&cfg.trig_mask0_header, DS_CFG_TRIG_MASK0);
176 WL32(&cfg.trig_mask1_header, DS_CFG_TRIG_MASK1);
177 WL32(&cfg.trig_value0_header, DS_CFG_TRIG_VALUE0);
178 WL32(&cfg.trig_value1_header, DS_CFG_TRIG_VALUE1);
179 WL32(&cfg.trig_edge0_header, DS_CFG_TRIG_EDGE0);
180 WL32(&cfg.trig_edge1_header, DS_CFG_TRIG_EDGE1);
181 WL32(&cfg.trig_count0_header, DS_CFG_TRIG_COUNT0);
182 WL32(&cfg.trig_count1_header, DS_CFG_TRIG_COUNT1);
183 WL32(&cfg.trig_logic0_header, DS_CFG_TRIG_LOGIC0);
184 WL32(&cfg.trig_logic1_header, DS_CFG_TRIG_LOGIC1);
185 WL32(&cfg.end_sync, DS_CFG_END);
187 /* Pass in the length of a fixed-size struct. Really. */
188 len = sizeof(struct dslogic_fpga_config) / 2;
190 c[1] = (len >> 8) & 0xff;
191 c[2] = (len >> 16) & 0xff;
193 ret = libusb_control_transfer(usb->devhdl, LIBUSB_REQUEST_TYPE_VENDOR |
194 LIBUSB_ENDPOINT_OUT, DS_CMD_CONFIG, 0x0000, 0x0000,
197 sr_err("Failed to send FPGA configure command: %s.", libusb_error_name(ret));
202 * 15 1 = internal test mode
203 * 14 1 = external test mode
204 * 13 1 = loopback test mode
207 * 6 1 = samplerate 400MHz
208 * 5 1 = samplerate 200MHz or analog mode
209 * 4 0 = logic, 1 = dso or analog
211 * 1 0 = internal clock, 1 = external clock
212 * 0 1 = trigger enabled
215 if (devc->dslogic_mode == DS_OP_INTERNAL_TEST)
217 else if (devc->dslogic_mode == DS_OP_EXTERNAL_TEST)
219 else if (devc->dslogic_mode == DS_OP_LOOPBACK_TEST)
221 if (devc->dslogic_external_clock)
223 WL16(&cfg.mode, v16);
225 v32 = ceil(SR_MHZ(100) * 1.0 / devc->cur_samplerate);
226 WL32(&cfg.divider, v32);
227 WL32(&cfg.count, devc->limit_samples);
229 len = sizeof(struct dslogic_fpga_config);
230 ret = libusb_bulk_transfer(usb->devhdl, 2 | LIBUSB_ENDPOINT_OUT,
231 (unsigned char *)&cfg, len, &transferred, USB_TIMEOUT);
232 if (ret < 0 || transferred != len) {
233 sr_err("Failed to send FPGA configuration: %s.", libusb_error_name(ret));