2 * This file is part of the libsigrok project.
4 * Copyright (C) 2013 Bert Vermeulen <bert@biot.com>
5 * Copyright (C) 2012 Joel Holdsworth <joel@airwebreathe.org.uk>
7 * This program is free software: you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation, either version 3 of the License, or
10 * (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program. If not, see <http://www.gnu.org/licenses/>.
24 #include <glib/gstdio.h>
29 * This should be larger than the FPGA bitstream image so that it'll get
30 * uploaded in one big operation. There seem to be issues when uploading
33 #define FW_BUFSIZE (1024 * 1024)
35 #define FPGA_UPLOAD_DELAY (10 * 1000)
37 #define USB_TIMEOUT (3 * 1000)
39 SR_PRIV int dslogic_set_vth(const struct sr_dev_inst *sdi, double vth)
41 struct sr_usb_dev_inst *usb;
43 const uint8_t value = (vth / 5.0) * 255;
44 const uint16_t cmd = value | (DS_ADDR_VTH << 8);
48 /* Send the control command. */
49 ret = libusb_control_transfer(usb->devhdl,
50 LIBUSB_REQUEST_TYPE_VENDOR | LIBUSB_ENDPOINT_OUT,
51 DS_CMD_WR_REG, 0x0000, 0x0000,
52 (unsigned char *)&cmd, sizeof(cmd), 3000);
54 sr_err("Unable to send VTH command: %s.",
55 libusb_error_name(ret));
62 SR_PRIV int dslogic_fpga_firmware_upload(const struct sr_dev_inst *sdi,
66 struct sr_resource bitstream;
67 struct drv_context *drvc;
68 struct sr_usb_dev_inst *usb;
73 const uint8_t cmd[3] = {0, 0, 0};
75 drvc = sdi->driver->context;
78 sr_dbg("Uploading FPGA firmware '%s'.", name);
80 result = sr_resource_open(drvc->sr_ctx, &bitstream,
81 SR_RESOURCE_FIRMWARE, name);
85 /* Tell the device firmware is coming. */
86 if ((ret = libusb_control_transfer(usb->devhdl, LIBUSB_REQUEST_TYPE_VENDOR |
87 LIBUSB_ENDPOINT_OUT, DS_CMD_CONFIG, 0x0000, 0x0000,
88 (unsigned char *)&cmd, sizeof(cmd), USB_TIMEOUT)) < 0) {
89 sr_err("Failed to upload FPGA firmware: %s.", libusb_error_name(ret));
90 sr_resource_close(drvc->sr_ctx, &bitstream);
94 /* Give the FX2 time to get ready for FPGA firmware upload. */
95 g_usleep(FPGA_UPLOAD_DELAY);
97 buf = g_malloc(FW_BUFSIZE);
101 chunksize = sr_resource_read(drvc->sr_ctx, &bitstream,
108 if ((ret = libusb_bulk_transfer(usb->devhdl, 2 | LIBUSB_ENDPOINT_OUT,
109 buf, chunksize, &transferred, USB_TIMEOUT)) < 0) {
110 sr_err("Unable to configure FPGA firmware: %s.",
111 libusb_error_name(ret));
116 sr_spew("Uploaded %" PRIu64 "/%" PRIu64 " bytes.",
117 sum, bitstream.size);
119 if (transferred != chunksize) {
120 sr_err("Short transfer while uploading FPGA firmware.");
126 sr_resource_close(drvc->sr_ctx, &bitstream);
129 sr_dbg("FPGA firmware upload done.");
134 SR_PRIV int dslogic_start_acquisition(const struct sr_dev_inst *sdi)
136 struct dev_context *devc;
137 struct sr_usb_dev_inst *usb;
138 struct dslogic_mode mode;
142 mode.flags = DS_START_FLAGS_MODE_LA;
143 mode.sample_delay_h = mode.sample_delay_l = 0;
144 if (devc->sample_wide)
145 mode.flags |= DS_START_FLAGS_SAMPLE_WIDE;
148 ret = libusb_control_transfer(usb->devhdl, LIBUSB_REQUEST_TYPE_VENDOR |
149 LIBUSB_ENDPOINT_OUT, DS_CMD_START, 0x0000, 0x0000,
150 (unsigned char *)&mode, sizeof(mode), USB_TIMEOUT);
152 sr_err("Failed to send start command: %s.", libusb_error_name(ret));
159 SR_PRIV int dslogic_stop_acquisition(const struct sr_dev_inst *sdi)
161 struct sr_usb_dev_inst *usb;
162 struct dslogic_mode mode;
165 mode.flags = DS_START_FLAGS_STOP;
166 mode.sample_delay_h = mode.sample_delay_l = 0;
169 ret = libusb_control_transfer(usb->devhdl, LIBUSB_REQUEST_TYPE_VENDOR |
170 LIBUSB_ENDPOINT_OUT, DS_CMD_START, 0x0000, 0x0000,
171 (unsigned char *)&mode, sizeof(struct dslogic_mode), USB_TIMEOUT);
173 sr_err("Failed to send stop command: %s.", libusb_error_name(ret));
181 * Get the session trigger and configure the FPGA structure
184 static int dslogic_set_trigger(const struct sr_dev_inst *sdi,
185 struct dslogic_fpga_config *cfg)
187 struct sr_trigger *trigger;
188 struct sr_trigger_stage *stage;
189 struct sr_trigger_match *match;
190 struct dev_context *devc;
192 int channelbit, i = 0;
198 for (l = sdi->channels; l; l = l->next) {
199 const struct sr_channel *const probe = (struct sr_channel *)l->data;
200 cfg->ch_en |= probe->enabled << probe->index;
203 cfg->trig_mask0[0] = 0xffff;
204 cfg->trig_mask1[0] = 0xffff;
206 cfg->trig_value0[0] = 0;
207 cfg->trig_value1[0] = 0;
209 cfg->trig_edge0[0] = 0;
210 cfg->trig_edge1[0] = 0;
212 cfg->trig_logic0[0] = 0;
213 cfg->trig_logic1[0] = 0;
215 cfg->trig_count[0] = 0;
219 for (i = 1; i < DS_NUM_TRIGGER_STAGES; i++) {
220 cfg->trig_mask0[i] = 0xff;
221 cfg->trig_mask1[i] = 0xff;
222 cfg->trig_value0[i] = 0;
223 cfg->trig_value1[i] = 0;
224 cfg->trig_edge0[i] = 0;
225 cfg->trig_edge1[i] = 0;
226 cfg->trig_logic0[i] = 2;
227 cfg->trig_logic1[i] = 2;
228 cfg->trig_count[i] = 0;
231 cfg->trig_pos = (uint32_t)(devc->capture_ratio / 100.0 * devc->limit_samples);
232 sr_dbg("pos: %d", cfg->trig_pos);
234 sr_dbg("configuring trigger");
236 if (!(trigger = sr_session_trigger_get(sdi->session))) {
237 sr_dbg("No session trigger found");
241 for (l = trigger->stages; l; l = l->next) {
243 for (m = stage->matches; m; m = m->next) {
245 if (!match->channel->enabled)
246 /* Ignore disabled channels with a trigger. */
248 channelbit = 1 << (match->channel->index);
249 /* Simple trigger support (event). */
250 if (match->match == SR_TRIGGER_ONE) {
251 cfg->trig_mask0[0] &= ~channelbit;
252 cfg->trig_mask1[0] &= ~channelbit;
253 cfg->trig_value0[0] |= channelbit;
254 cfg->trig_value1[0] |= channelbit;
255 } else if (match->match == SR_TRIGGER_ZERO) {
256 cfg->trig_mask0[0] &= ~channelbit;
257 cfg->trig_mask1[0] &= ~channelbit;
258 } else if (match->match == SR_TRIGGER_FALLING) {
259 cfg->trig_mask0[0] &= ~channelbit;
260 cfg->trig_mask1[0] &= ~channelbit;
261 cfg->trig_edge0[0] |= channelbit;
262 cfg->trig_edge1[0] |= channelbit;
263 } else if (match->match == SR_TRIGGER_RISING) {
264 cfg->trig_mask0[0] &= ~channelbit;
265 cfg->trig_mask1[0] &= ~channelbit;
266 cfg->trig_value0[0] |= channelbit;
267 cfg->trig_value1[0] |= channelbit;
268 cfg->trig_edge0[0] |= channelbit;
269 cfg->trig_edge1[0] |= channelbit;
270 } else if (match->match == SR_TRIGGER_EDGE) {
271 cfg->trig_edge0[0] |= channelbit;
272 cfg->trig_edge1[0] |= channelbit;
277 v16 = RL16(&cfg->mode);
279 WL16(&cfg->mode, v16);
284 SR_PRIV int dslogic_fpga_configure(const struct sr_dev_inst *sdi)
286 struct dev_context *devc;
287 struct sr_usb_dev_inst *usb;
289 struct dslogic_fpga_config cfg;
292 int transferred, len, ret;
294 sr_dbg("Configuring FPGA.");
299 WL32(&cfg.sync, DS_CFG_START);
300 WL16(&cfg.mode_header, DS_CFG_MODE);
301 WL16(&cfg.divider_header, DS_CFG_DIVIDER);
302 WL16(&cfg.count_header, DS_CFG_COUNT);
303 WL16(&cfg.trig_pos_header, DS_CFG_TRIG_POS);
304 WL16(&cfg.trig_glb_header, DS_CFG_TRIG_GLB);
305 WL16(&cfg.ch_en_header, DS_CFG_CH_EN);
306 WL16(&cfg.trig_header, DS_CFG_TRIG);
307 WL32(&cfg.end_sync, DS_CFG_END);
309 /* Pass in the length of a fixed-size struct. Really. */
310 len = sizeof(struct dslogic_fpga_config) / 2;
312 c[1] = (len >> 8) & 0xff;
313 c[2] = (len >> 16) & 0xff;
315 ret = libusb_control_transfer(usb->devhdl, LIBUSB_REQUEST_TYPE_VENDOR |
316 LIBUSB_ENDPOINT_OUT, DS_CMD_SETTING, 0x0000, 0x0000,
317 c, sizeof(c), USB_TIMEOUT);
319 sr_err("Failed to send FPGA configure command: %s.",
320 libusb_error_name(ret));
326 if (devc->dslogic_mode == DS_OP_INTERNAL_TEST)
327 v16 = DS_MODE_INT_TEST;
328 else if (devc->dslogic_mode == DS_OP_EXTERNAL_TEST)
329 v16 = DS_MODE_EXT_TEST;
330 else if (devc->dslogic_mode == DS_OP_LOOPBACK_TEST)
331 v16 = DS_MODE_LPB_TEST;
332 if (devc->dslogic_continuous_mode)
333 v16 |= DS_MODE_STREAM_MODE;
334 if (devc->dslogic_external_clock) {
335 v16 |= DS_MODE_CLK_TYPE;
336 if (devc->dslogic_clock_edge == DS_EDGE_FALLING)
337 v16 |= DS_MODE_CLK_EDGE;
339 if (devc->limit_samples > DS_MAX_LOGIC_DEPTH *
340 ceil(devc->cur_samplerate * 1.0 / DS_MAX_LOGIC_SAMPLERATE)
341 && !devc->dslogic_continuous_mode) {
342 /* Enable RLE for long captures.
343 * Without this, captured data present errors.
345 v16 |= DS_MODE_RLE_MODE;
348 WL16(&cfg.mode, v16);
349 v32 = ceil(DS_MAX_LOGIC_SAMPLERATE * 1.0 / devc->cur_samplerate);
350 WL32(&cfg.divider, v32);
351 WL32(&cfg.count, devc->limit_samples);
353 dslogic_set_trigger(sdi, &cfg);
355 len = sizeof(struct dslogic_fpga_config);
356 ret = libusb_bulk_transfer(usb->devhdl, 2 | LIBUSB_ENDPOINT_OUT,
357 (unsigned char *)&cfg, len, &transferred, USB_TIMEOUT);
358 if (ret < 0 || transferred != len) {
359 sr_err("Failed to send FPGA configuration: %s.", libusb_error_name(ret));
366 static int to_bytes_per_ms(struct dev_context *devc)
368 if (devc->cur_samplerate > SR_MHZ(100))
369 return SR_MHZ(100) / 1000 * (devc->sample_wide ? 2 : 1);
371 return devc->cur_samplerate / 1000 * (devc->sample_wide ? 2 : 1);
374 static size_t get_buffer_size(struct dev_context *devc)
379 * The buffer should be large enough to hold 10ms of data and
382 s = 10 * to_bytes_per_ms(devc);
383 // s = to_bytes_per_ms(devc->cur_samplerate);
384 return (s + 511) & ~511;
387 SR_PRIV int dslogic_get_number_of_transfers(struct dev_context *devc)
391 /* Total buffer size should be able to hold about 100ms of data. */
392 n = (100 * to_bytes_per_ms(devc) / get_buffer_size(devc));
393 sr_info("New calculation: %d", n);
395 if (n > NUM_SIMUL_TRANSFERS)
396 return NUM_SIMUL_TRANSFERS;