2 * This file is part of the libsigrok project.
4 * Copyright (C) 2013 Bert Vermeulen <bert@biot.com>
5 * Copyright (C) 2012 Joel Holdsworth <joel@airwebreathe.org.uk>
7 * This program is free software: you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation, either version 3 of the License, or
10 * (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program. If not, see <http://www.gnu.org/licenses/>.
21 #include <sys/types.h>
27 #include <glib/gstdio.h>
31 #define FW_BUFSIZE (4 * 1024)
33 #define FPGA_UPLOAD_DELAY (10 * 1000)
35 #define USB_TIMEOUT (3 * 1000)
37 int dslogic_fpga_firmware_upload(const struct sr_dev_inst *sdi,
42 struct sr_usb_dev_inst *usb;
43 int chunksize, result, ret;
48 sr_dbg("Uploading FPGA firmware at %s.", filename);
51 if (stat(filename, &st) < 0) {
52 sr_err("Unable to upload FPGA firmware: %s", strerror(errno));
56 /* Tell the device firmware is coming. */
57 memset(cmd, 0, sizeof(cmd));
58 if ((ret = libusb_control_transfer(usb->devhdl, LIBUSB_REQUEST_TYPE_VENDOR |
59 LIBUSB_ENDPOINT_OUT, DS_CMD_FPGA_FW, 0x0000, 0x0000,
60 (unsigned char *)&cmd, sizeof(cmd), USB_TIMEOUT)) < 0) {
61 sr_err("Failed to upload FPGA firmware: %s.", libusb_error_name(ret));
64 buf = g_malloc(FW_BUFSIZE);
66 if (!(fw = g_fopen(filename, "rb"))) {
67 sr_err("Unable to open %s for reading: %s.", filename, strerror(errno));
71 /* Give the FX2 time to get ready for FPGA firmware upload. */
72 g_usleep(FPGA_UPLOAD_DELAY);
77 if ((chunksize = fread(buf, 1, FW_BUFSIZE, fw)) == 0)
80 if ((ret = libusb_bulk_transfer(usb->devhdl, 2 | LIBUSB_ENDPOINT_OUT,
81 buf, chunksize, &transferred, USB_TIMEOUT)) < 0) {
82 sr_err("Unable to configure FPGA firmware: %s.",
83 libusb_error_name(ret));
88 sr_spew("Uploaded %d/%d bytes.", sum, st.st_size);
90 if (transferred != chunksize) {
91 sr_err("Short transfer while uploading FPGA firmware.");
99 sr_dbg("FPGA firmware upload done.");
104 int dslogic_start_acquisition(const struct sr_dev_inst *sdi)
106 struct dev_context *devc;
107 struct sr_usb_dev_inst *usb;
108 struct dslogic_mode mode;
113 mode.sample_delay_h = mode.sample_delay_l = 0;
114 if (devc->sample_wide)
115 mode.flags |= DS_START_FLAGS_SAMPLE_WIDE;
118 ret = libusb_control_transfer(usb->devhdl, LIBUSB_REQUEST_TYPE_VENDOR |
119 LIBUSB_ENDPOINT_OUT, DS_CMD_START, 0x0000, 0x0000,
120 (unsigned char *)&mode, sizeof(mode), USB_TIMEOUT);
122 sr_err("Failed to send start command: %s.", libusb_error_name(ret));
129 int dslogic_stop_acquisition(const struct sr_dev_inst *sdi)
131 struct sr_usb_dev_inst *usb;
132 struct dslogic_mode mode;
135 mode.flags = DS_START_FLAGS_STOP;
136 mode.sample_delay_h = mode.sample_delay_l = 0;
139 ret = libusb_control_transfer(usb->devhdl, LIBUSB_REQUEST_TYPE_VENDOR |
140 LIBUSB_ENDPOINT_OUT, DS_CMD_START, 0x0000, 0x0000,
141 (unsigned char *)&mode, sizeof(struct dslogic_mode), USB_TIMEOUT);
143 sr_err("Failed to send stop command: %s.", libusb_error_name(ret));
150 int dslogic_fpga_configure(const struct sr_dev_inst *sdi)
152 struct dev_context *devc;
153 struct sr_usb_dev_inst *usb;
155 struct dslogic_fpga_config cfg;
158 int transferred, len, ret;
160 sr_dbg("Configuring FPGA.");
164 WL32(&cfg.sync, DS_CFG_START);
165 WL16(&cfg.mode_header, DS_CFG_MODE);
166 WL32(&cfg.divider_header, DS_CFG_DIVIDER);
167 WL32(&cfg.count_header, DS_CFG_COUNT);
168 WL32(&cfg.trig_pos_header, DS_CFG_TRIG_POS);
169 WL16(&cfg.trig_glb_header, DS_CFG_TRIG_GLB);
170 WL32(&cfg.trig_adp_header, DS_CFG_TRIG_ADP);
171 WL32(&cfg.trig_sda_header, DS_CFG_TRIG_SDA);
172 WL32(&cfg.trig_mask0_header, DS_CFG_TRIG_MASK0);
173 WL32(&cfg.trig_mask1_header, DS_CFG_TRIG_MASK1);
174 WL32(&cfg.trig_value0_header, DS_CFG_TRIG_VALUE0);
175 WL32(&cfg.trig_value1_header, DS_CFG_TRIG_VALUE1);
176 WL32(&cfg.trig_edge0_header, DS_CFG_TRIG_EDGE0);
177 WL32(&cfg.trig_edge1_header, DS_CFG_TRIG_EDGE1);
178 WL32(&cfg.trig_count0_header, DS_CFG_TRIG_COUNT0);
179 WL32(&cfg.trig_count1_header, DS_CFG_TRIG_COUNT1);
180 WL32(&cfg.trig_logic0_header, DS_CFG_TRIG_LOGIC0);
181 WL32(&cfg.trig_logic1_header, DS_CFG_TRIG_LOGIC1);
182 WL32(&cfg.end_sync, DS_CFG_END);
184 /* Pass in the length of a fixed-size struct. Really. */
185 len = sizeof(struct dslogic_fpga_config) / 2;
187 c[1] = (len >> 8) & 0xff;
188 c[2] = (len >> 16) & 0xff;
190 ret = libusb_control_transfer(usb->devhdl, LIBUSB_REQUEST_TYPE_VENDOR |
191 LIBUSB_ENDPOINT_OUT, DS_CMD_CONFIG, 0x0000, 0x0000,
194 sr_err("Failed to send FPGA configure command: %s.", libusb_error_name(ret));
199 * 15 1 = internal test mode
200 * 14 1 = external test mode
201 * 13 1 = loopback test mode
204 * 6 1 = samplerate 400MHz
205 * 5 1 = samplerate 200MHz or analog mode
206 * 4 0 = logic, 1 = dso or analog
208 * 1 0 = internal clock, 1 = external clock
209 * 0 1 = trigger enabled
212 if (devc->dslogic_mode == DS_OP_INTERNAL_TEST)
214 else if (devc->dslogic_mode == DS_OP_EXTERNAL_TEST)
216 else if (devc->dslogic_mode == DS_OP_LOOPBACK_TEST)
218 if (devc->dslogic_external_clock)
220 WL16(&cfg.mode, v16);
222 v32 = ceil(SR_MHZ(100) * 1.0 / devc->cur_samplerate);
223 WL32(&cfg.divider, v32);
224 WL32(&cfg.count, devc->limit_samples);
226 len = sizeof(struct dslogic_fpga_config);
227 ret = libusb_bulk_transfer(usb->devhdl, 2 | LIBUSB_ENDPOINT_OUT,
228 (unsigned char *)&cfg, len, &transferred, USB_TIMEOUT);
229 if (ret < 0 || transferred != len) {
230 sr_err("Failed to send FPGA configuration: %s.", libusb_error_name(ret));