2 * This file is part of the libsigrok project.
4 * Copyright (C) 2013 Bert Vermeulen <bert@biot.com>
5 * Copyright (C) 2012 Joel Holdsworth <joel@airwebreathe.org.uk>
7 * This program is free software: you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation, either version 3 of the License, or
10 * (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program. If not, see <http://www.gnu.org/licenses/>.
21 #ifndef LIBSIGROK_HARDWARE_DREAMSOURCELAB_DSLOGIC_PROTOCOL_H
22 #define LIBSIGROK_HARDWARE_DREAMSOURCELAB_DSLOGIC_PROTOCOL_H
29 #include <libsigrok/libsigrok.h>
30 #include "libsigrok-internal.h"
32 #define LOG_PREFIX "dreamsourcelab-dslogic"
34 #define USB_INTERFACE 0
35 #define USB_CONFIGURATION 1
37 #define MAX_RENUM_DELAY_MS 3000
38 #define NUM_SIMUL_TRANSFERS 32
39 #define MAX_EMPTY_TRANSFERS (NUM_SIMUL_TRANSFERS * 2)
41 #define NUM_CHANNELS 16
42 #define NUM_TRIGGER_STAGES 16
44 #define DSLOGIC_REQUIRED_VERSION_MAJOR 1
46 /* 6 delay states of up to 256 clock ticks */
47 #define MAX_SAMPLE_DELAY (6 * 256)
49 #define DSLOGIC_FPGA_FIRMWARE_5V "dreamsourcelab-dslogic-fpga-5v.fw"
50 #define DSLOGIC_FPGA_FIRMWARE_3V3 "dreamsourcelab-dslogic-fpga-3v3.fw"
51 #define DSCOPE_FPGA_FIRMWARE "dreamsourcelab-dscope-fpga.fw"
52 #define DSLOGIC_PRO_FPGA_FIRMWARE "dreamsourcelab-dslogic-pro-fpga.fw"
53 #define DSLOGIC_PLUS_FPGA_FIRMWARE "dreamsourcelab-dslogic-plus-fpga.fw"
54 #define DSLOGIC_BASIC_FPGA_FIRMWARE "dreamsourcelab-dslogic-basic-fpga.fw"
56 enum dslogic_operation_modes {
63 enum dslogic_edge_modes {
68 struct dslogic_version {
75 uint8_t sample_delay_h;
76 uint8_t sample_delay_l;
79 struct dslogic_trigger_pos {
83 uint32_t remain_cnt_l;
84 uint32_t remain_cnt_h;
86 uint8_t first_block[488];
89 struct dslogic_profile {
95 const char *model_version;
101 const char *usb_manufacturer;
102 const char *usb_product;
104 /* Memory depth in bits. */
109 const struct dslogic_profile *profile;
111 * Since we can't keep track of a DSLogic device after upgrading
112 * the firmware (it renumerates into a different device address
113 * after the upgrade) this is like a global lock. No device will open
114 * until a proper delay after the last device was upgraded.
118 const uint64_t *samplerates;
121 uint64_t cur_samplerate;
122 uint64_t limit_samples;
123 uint64_t capture_ratio;
125 gboolean acq_aborted;
127 unsigned int sent_samples;
128 int submitted_transfers;
129 int empty_transfer_count;
131 unsigned int num_transfers;
132 struct libusb_transfer **transfers;
133 struct sr_context *ctx;
135 uint16_t *deinterleave_buffer;
138 uint32_t trigger_pos;
139 gboolean external_clock;
140 gboolean continuous_mode;
142 double cur_threshold;
145 SR_PRIV int dslogic_fpga_firmware_upload(const struct sr_dev_inst *sdi);
146 SR_PRIV int dslogic_set_voltage_threshold(const struct sr_dev_inst *sdi, double threshold);
147 SR_PRIV int dslogic_dev_open(struct sr_dev_inst *sdi, struct sr_dev_driver *di);
148 SR_PRIV struct dev_context *dslogic_dev_new(void);
149 SR_PRIV int dslogic_acquisition_start(const struct sr_dev_inst *sdi);
150 SR_PRIV int dslogic_acquisition_stop(struct sr_dev_inst *sdi);