2 * This file is part of the libsigrok project.
4 * Copyright (C) 2010-2012 Håvard Espeland <gus@ping.uio.no>,
5 * Copyright (C) 2010 Martin Stensgård <mastensg@ping.uio.no>
6 * Copyright (C) 2010 Carl Henrik Lunde <chlunde@ping.uio.no>
8 * This program is free software: you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation, either version 3 of the License, or
11 * (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program. If not, see <http://www.gnu.org/licenses/>.
22 #ifndef LIBSIGROK_HARDWARE_ASIX_SIGMA_PROTOCOL_H
23 #define LIBSIGROK_HARDWARE_ASIX_SIGMA_PROTOCOL_H
30 #include <libsigrok/libsigrok.h>
31 #include "libsigrok-internal.h"
33 #define LOG_PREFIX "asix-sigma"
36 * Triggers are not working in this implementation. Stop claiming
37 * support for the feature which effectively is not available, until
38 * the implementation got fixed. Yet keep the code in place and allow
39 * developers to turn on this switch during development.
41 #define ASIX_SIGMA_WITH_TRIGGER 0
43 #define USB_VENDOR 0xa600
44 #define USB_PRODUCT 0xa000
45 #define USB_DESCRIPTION "ASIX SIGMA"
47 enum sigma_write_register {
48 WRITE_CLOCK_SELECT = 0,
49 WRITE_TRIGGER_SELECT0 = 1,
50 WRITE_TRIGGER_SELECT1 = 2,
53 WRITE_POST_TRIGGER = 5,
54 WRITE_TRIGGER_OPTION = 6,
60 enum sigma_read_register {
62 READ_TRIGGER_POS_LOW = 1,
63 READ_TRIGGER_POS_HIGH = 2,
64 READ_TRIGGER_POS_UP = 3,
65 READ_STOP_POS_LOW = 4,
66 READ_STOP_POS_HIGH = 5,
69 READ_PIN_CHANGE_LOW = 8,
70 READ_PIN_CHANGE_HIGH = 9,
71 READ_BLOCK_LAST_TS_LOW = 10,
72 READ_BLOCK_LAST_TS_HIGH = 11,
78 #define REG_ADDR_LOW (0x0 << 4)
79 #define REG_ADDR_HIGH (0x1 << 4)
80 #define REG_DATA_LOW (0x2 << 4)
81 #define REG_DATA_HIGH_WRITE (0x3 << 4)
82 #define REG_READ_ADDR (0x4 << 4)
83 #define REG_DRAM_WAIT_ACK (0x5 << 4)
85 /* Bit (1 << 4) can be low or high (double buffer / cache) */
86 #define REG_DRAM_BLOCK (0x6 << 4)
87 #define REG_DRAM_BLOCK_BEGIN (0x8 << 4)
88 #define REG_DRAM_BLOCK_DATA (0xa << 4)
95 #define EVENTS_PER_CLUSTER 7
97 #define CHUNK_SIZE 1024
99 /* WRITE_MODE register fields. */
100 #define WMR_SDRAMWRITEEN (1 << 0)
101 #define WMR_SDRAMREADEN (1 << 1)
102 #define WMR_TRGRES (1 << 2)
103 #define WMR_TRGEN (1 << 3)
104 #define WMR_FORCESTOP (1 << 4)
105 #define WMR_TRGSW (1 << 5)
106 /* not used: bit position 6 */
107 #define WMR_SDRAMINIT (1 << 7)
109 /* READ_MODE register fields. */
110 #define RMR_SDRAMWRITEEN (1 << 0)
111 #define RMR_SDRAMREADEN (1 << 1)
112 /* not used: bit position 2 */
113 #define RMR_TRGEN (1 << 3)
114 #define RMR_ROUND (1 << 4)
115 #define RMR_TRIGGERED (1 << 5)
116 #define RMR_POSTTRIGGERED (1 << 6)
117 /* not used: bit position 7 */
120 * Layout of the sample data DRAM, which will be downloaded to the PC:
122 * Sigma memory is organized in 32K rows. Each row contains 64 clusters.
123 * Each cluster contains a timestamp (16bit) and 7 samples (16bits each).
124 * Total memory size is 32K x 64 x 8 x 2 bytes == 32 MB (256 Mbit).
126 * Sample data is represented in 16bit quantities. The first sample in
127 * the cluster corresponds to the cluster's timestamp. Each next sample
128 * corresponds to the timestamp + 1, timestamp + 2, etc (the distance is
129 * one sample period, according to the samplerate). In the absence of
130 * pin level changes, no data is provided (RLE compression). A cluster
131 * is enforced for each 64K ticks of the timestamp, to reliably handle
132 * rollover and determination of the next timestamp of the next cluster.
134 * For samplerates of 100MHz, there is one 16 bit entity for each 20ns
135 * period (50MHz rate). The 16 bit memory contains 2 samples of up to
136 * 8 channels. Bits of multiple samples are interleaved. For samplerates
137 * of 200MHz one 16bit entity contains 4 samples of up to 4 channels,
140 * Memory addresses (sample count, trigger position) are kept in 24bit
141 * entities. The upper 15 bit refer to the "row", the lower 9 bit refer
142 * to the "event" within the row. Because there is one timestamp for
143 * seven samples each, one memory row can hold up to 64x7 == 448 samples.
146 /* One "DRAM cluster" contains a timestamp and 7 samples, 16b total. */
147 struct sigma_dram_cluster {
148 uint8_t timestamp_lo;
149 uint8_t timestamp_hi;
156 /* One "DRAM line" contains 64 "DRAM clusters", 1024b total. */
157 struct sigma_dram_line {
158 struct sigma_dram_cluster cluster[64];
161 struct clockselect_50 {
164 uint16_t disabled_channels;
167 /* The effect of all these are still a bit unclear. */
168 struct triggerinout {
169 uint8_t trgout_resistor_enable : 1;
170 uint8_t trgout_resistor_pullup : 1;
171 uint8_t reserved1 : 1;
172 uint8_t trgout_bytrigger : 1;
173 uint8_t trgout_byevent : 1;
174 uint8_t trgout_bytriggerin : 1;
175 uint8_t reserved2 : 2;
177 /* Should be set same as the first two */
178 uint8_t trgout_resistor_enable2 : 1;
179 uint8_t trgout_resistor_pullup2 : 1;
181 uint8_t reserved3 : 1;
182 uint8_t trgout_long : 1;
183 uint8_t trgout_pin : 1; /* Use 1k resistor. Pullup? */
184 uint8_t trgin_negate : 1;
185 uint8_t trgout_enable : 1;
186 uint8_t trgin_enable : 1;
190 /* The actual LUTs. */
191 uint16_t m0d[4], m1d[4], m2d[4];
192 uint16_t m3, m3s, m4;
194 /* Parameters should be sent as a single register write. */
197 uint8_t selpresc : 6;
209 /* Trigger configuration */
210 struct sigma_trigger {
211 /* Only two channels can be used in mask. */
213 uint16_t fallingmask;
215 /* Simple trigger support (<= 50 MHz). */
217 uint16_t simplevalue;
219 /* TODO: Advanced trigger support (boolean expressions). */
222 /* Events for trigger operation. */
234 /* Logical functions for trigger operation. */
246 SIGMA_UNINITIALIZED = 0,
257 struct ftdi_context ftdic;
258 uint64_t cur_samplerate;
260 uint64_t limit_samples;
261 uint64_t sent_samples;
266 int samples_per_event;
268 struct sigma_trigger trigger;
270 struct sigma_state state;
273 extern SR_PRIV const uint64_t samplerates[];
274 extern SR_PRIV const size_t samplerates_count;
276 SR_PRIV int sigma_write_register(uint8_t reg, uint8_t *data, size_t len,
277 struct dev_context *devc);
278 SR_PRIV int sigma_set_register(uint8_t reg, uint8_t value, struct dev_context *devc);
279 SR_PRIV int sigma_write_trigger_lut(struct triggerlut *lut, struct dev_context *devc);
280 SR_PRIV uint64_t sigma_limit_samples_to_msec(const struct dev_context *devc,
281 uint64_t limit_samples);
282 SR_PRIV int sigma_set_samplerate(const struct sr_dev_inst *sdi, uint64_t samplerate);
283 SR_PRIV int sigma_convert_trigger(const struct sr_dev_inst *sdi);
284 SR_PRIV int sigma_receive_data(int fd, int revents, void *cb_data);
285 SR_PRIV int sigma_build_basic_trigger(struct triggerlut *lut, struct dev_context *devc);