2 * This file is part of the libsigrok project.
4 * Copyright (C) 2010-2012 Håvard Espeland <gus@ping.uio.no>,
5 * Copyright (C) 2010 Martin Stensgård <mastensg@ping.uio.no>
6 * Copyright (C) 2010 Carl Henrik Lunde <chlunde@ping.uio.no>
7 * Copyright (C) 2020 Gerhard Sittig <gerhard.sittig@gmx.net>
9 * This program is free software: you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation, either version 3 of the License, or
12 * (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program. If not, see <http://www.gnu.org/licenses/>.
24 * ASIX SIGMA/SIGMA2 logic analyzer driver
31 * The ASIX SIGMA hardware supports fixed 200MHz and 100MHz sample rates
32 * (by means of separate firmware images). As well as 50MHz divided by
33 * an integer divider in the 1..256 range (by the "typical" firmware).
34 * Which translates to a strict lower boundary of around 195kHz.
36 * This driver "suggests" a subset of the available rates by listing a
37 * few discrete values, while setter routines accept any user specified
38 * rate that is supported by the hardware.
40 static const uint64_t samplerates[] = {
41 /* 50MHz and integer divider. 1/2/5 steps (where possible). */
42 SR_KHZ(200), SR_KHZ(500),
43 SR_MHZ(1), SR_MHZ(2), SR_MHZ(5),
44 SR_MHZ(10), SR_MHZ(25), SR_MHZ(50),
45 /* 100MHz/200MHz, fixed rates in special firmware. */
46 SR_MHZ(100), SR_MHZ(200),
49 SR_PRIV GVariant *sigma_get_samplerates_list(void)
51 return std_gvar_samplerates(samplerates, ARRAY_SIZE(samplerates));
54 static const char *firmware_files[] = {
55 [SIGMA_FW_50MHZ] = "asix-sigma-50.fw", /* 50MHz, 8bit divider. */
56 [SIGMA_FW_100MHZ] = "asix-sigma-100.fw", /* 100MHz, fixed. */
57 [SIGMA_FW_200MHZ] = "asix-sigma-200.fw", /* 200MHz, fixed. */
58 [SIGMA_FW_SYNC] = "asix-sigma-50sync.fw", /* Sync from external pin. */
59 [SIGMA_FW_FREQ] = "asix-sigma-phasor.fw", /* Frequency counter. */
62 #define SIGMA_FIRMWARE_SIZE_LIMIT (256 * 1024)
64 static int sigma_ftdi_open(const struct sr_dev_inst *sdi)
66 struct dev_context *devc;
75 if (devc->ftdi.is_open)
80 serno = sdi->serial_num;
81 if (!vid || !pid || !serno || !*serno)
84 ret = ftdi_init(&devc->ftdi.ctx);
86 sr_err("Cannot initialize FTDI context (%d): %s.",
87 ret, ftdi_get_error_string(&devc->ftdi.ctx));
90 ret = ftdi_usb_open_desc_index(&devc->ftdi.ctx,
91 vid, pid, NULL, serno, 0);
93 sr_err("Cannot open device (%d): %s.",
94 ret, ftdi_get_error_string(&devc->ftdi.ctx));
97 devc->ftdi.is_open = TRUE;
102 static int sigma_ftdi_close(struct dev_context *devc)
106 ret = ftdi_usb_close(&devc->ftdi.ctx);
107 devc->ftdi.is_open = FALSE;
108 devc->ftdi.must_close = FALSE;
109 ftdi_deinit(&devc->ftdi.ctx);
111 return ret == 0 ? SR_OK : SR_ERR_IO;
114 SR_PRIV int sigma_check_open(const struct sr_dev_inst *sdi)
116 struct dev_context *devc;
125 if (devc->ftdi.is_open)
128 ret = sigma_ftdi_open(sdi);
131 devc->ftdi.must_close = TRUE;
136 SR_PRIV int sigma_check_close(struct dev_context *devc)
143 if (devc->ftdi.must_close) {
144 ret = sigma_ftdi_close(devc);
147 devc->ftdi.must_close = FALSE;
153 SR_PRIV int sigma_force_open(const struct sr_dev_inst *sdi)
155 struct dev_context *devc;
164 ret = sigma_ftdi_open(sdi);
167 devc->ftdi.must_close = FALSE;
172 SR_PRIV int sigma_force_close(struct dev_context *devc)
174 return sigma_ftdi_close(devc);
178 * BEWARE! Error propagation is important, as are kinds of return values.
180 * - Raw USB tranport communicates the number of sent or received bytes,
181 * or negative error codes in the external library's(!) range of codes.
182 * - Internal routines at the "sigrok driver level" communicate success
183 * or failure in terms of SR_OK et al error codes.
184 * - Main loop style receive callbacks communicate booleans which arrange
185 * for repeated calls to drive progress during acquisition.
187 * Careful consideration by maintainers is essential, because all of the
188 * above kinds of values are assignment compatbile from the compiler's
189 * point of view. Implementation errors will go unnoticed at build time.
192 static int sigma_read_raw(struct dev_context *devc, void *buf, size_t size)
196 ret = ftdi_read_data(&devc->ftdi.ctx, (unsigned char *)buf, size);
198 sr_err("USB data read failed: %s",
199 ftdi_get_error_string(&devc->ftdi.ctx));
205 static int sigma_write_raw(struct dev_context *devc, const void *buf, size_t size)
209 ret = ftdi_write_data(&devc->ftdi.ctx, buf, size);
211 sr_err("USB data write failed: %s",
212 ftdi_get_error_string(&devc->ftdi.ctx));
213 } else if ((size_t)ret != size) {
214 sr_err("USB data write length mismatch.");
220 static int sigma_read_sr(struct dev_context *devc, void *buf, size_t size)
224 ret = sigma_read_raw(devc, buf, size);
225 if (ret < 0 || (size_t)ret != size)
231 static int sigma_write_sr(struct dev_context *devc, const void *buf, size_t size)
235 ret = sigma_write_raw(devc, buf, size);
236 if (ret < 0 || (size_t)ret != size)
243 * Implementor's note: The local write buffer's size shall suffice for
244 * any know FPGA register transaction that is involved in the supported
245 * feature set of this sigrok device driver. If the length check trips,
246 * that's a programmer's error and needs adjustment in the complete call
247 * stack of the respective code path.
249 #define SIGMA_MAX_REG_DEPTH 32
252 * Implementor's note: The FPGA command set supports register access
253 * with automatic address adjustment. This operation is documented to
254 * wrap within a 16-address range, it cannot cross boundaries where the
255 * register address' nibble overflows. An internal helper assumes that
256 * callers remain within this auto-adjustment range, and thus multi
257 * register access requests can never exceed that count.
259 #define SIGMA_MAX_REG_COUNT 16
261 SR_PRIV int sigma_write_register(struct dev_context *devc,
262 uint8_t reg, uint8_t *data, size_t len)
264 uint8_t buf[2 + SIGMA_MAX_REG_DEPTH * 2], *wrptr;
267 if (len > SIGMA_MAX_REG_DEPTH) {
268 sr_err("Short write buffer for %zu bytes to reg %u.", len, reg);
273 write_u8_inc(&wrptr, REG_ADDR_LOW | LO4(reg));
274 write_u8_inc(&wrptr, REG_ADDR_HIGH | HI4(reg));
275 for (idx = 0; idx < len; idx++) {
276 write_u8_inc(&wrptr, REG_DATA_LOW | LO4(data[idx]));
277 write_u8_inc(&wrptr, REG_DATA_HIGH_WRITE | HI4(data[idx]));
280 return sigma_write_sr(devc, buf, wrptr - buf);
283 SR_PRIV int sigma_set_register(struct dev_context *devc,
284 uint8_t reg, uint8_t value)
286 return sigma_write_register(devc, reg, &value, sizeof(value));
289 static int sigma_read_register(struct dev_context *devc,
290 uint8_t reg, uint8_t *data, size_t len)
292 uint8_t buf[3], *wrptr;
296 write_u8_inc(&wrptr, REG_ADDR_LOW | LO4(reg));
297 write_u8_inc(&wrptr, REG_ADDR_HIGH | HI4(reg));
298 write_u8_inc(&wrptr, REG_READ_ADDR);
299 ret = sigma_write_sr(devc, buf, wrptr - buf);
303 return sigma_read_sr(devc, data, len);
306 static int sigma_get_register(struct dev_context *devc,
307 uint8_t reg, uint8_t *data)
309 return sigma_read_register(devc, reg, data, sizeof(*data));
312 static int sigma_get_registers(struct dev_context *devc,
313 uint8_t reg, uint8_t *data, size_t count)
315 uint8_t buf[2 + SIGMA_MAX_REG_COUNT], *wrptr;
319 if (count > SIGMA_MAX_REG_COUNT) {
320 sr_err("Short command buffer for %zu reg reads at %u.", count, reg);
325 write_u8_inc(&wrptr, REG_ADDR_LOW | LO4(reg));
326 write_u8_inc(&wrptr, REG_ADDR_HIGH | HI4(reg));
327 for (idx = 0; idx < count; idx++)
328 write_u8_inc(&wrptr, REG_READ_ADDR | REG_ADDR_INC);
329 ret = sigma_write_sr(devc, buf, wrptr - buf);
333 return sigma_read_sr(devc, data, count);
336 static int sigma_read_pos(struct dev_context *devc,
337 uint32_t *stoppos, uint32_t *triggerpos, uint8_t *mode)
340 const uint8_t *rdptr;
346 * Read 7 registers starting at trigger position LSB.
347 * Which yields two 24bit counter values, and mode flags.
349 ret = sigma_get_registers(devc, READ_TRIGGER_POS_LOW,
350 result, sizeof(result));
355 v32 = read_u24le_inc(&rdptr);
358 v32 = read_u24le_inc(&rdptr);
361 v8 = read_u8_inc(&rdptr);
366 * These positions consist of "the memory row" in the MSB fields,
367 * and "an event index" within the row in the LSB fields. Part
368 * of the memory row's content is sample data, another part is
371 * The retrieved register values point to after the captured
372 * position. So they need to get decremented, and adjusted to
373 * cater for the timestamps when the decrement carries over to
374 * a different memory row.
376 if (stoppos && (--*stoppos & ROW_MASK) == ROW_MASK)
377 *stoppos -= CLUSTERS_PER_ROW;
378 if (triggerpos && (--*triggerpos & ROW_MASK) == ROW_MASK)
379 *triggerpos -= CLUSTERS_PER_ROW;
384 static int sigma_read_dram(struct dev_context *devc,
385 size_t startchunk, size_t numchunks, uint8_t *data)
387 uint8_t buf[128], *wrptr, regval;
392 if (2 + 3 * numchunks > ARRAY_SIZE(buf)) {
393 sr_err("Short write buffer for %zu DRAM row reads.", numchunks);
397 /* Communicate DRAM start address (memory row, aka samples line). */
399 write_u16be_inc(&wrptr, startchunk);
400 ret = sigma_write_register(devc, WRITE_MEMROW, buf, wrptr - buf);
405 * Access DRAM content. Fetch from DRAM to FPGA's internal RAM,
406 * then transfer via USB. Interleave the FPGA's DRAM access and
407 * USB transfer, use alternating buffers (0/1) in the process.
410 write_u8_inc(&wrptr, REG_DRAM_BLOCK);
411 write_u8_inc(&wrptr, REG_DRAM_WAIT_ACK);
412 for (chunk = 0; chunk < numchunks; chunk++) {
414 is_last = chunk == numchunks - 1;
416 regval = REG_DRAM_BLOCK | REG_DRAM_SEL_BOOL(!sel);
417 write_u8_inc(&wrptr, regval);
419 regval = REG_DRAM_BLOCK_DATA | REG_DRAM_SEL_BOOL(sel);
420 write_u8_inc(&wrptr, regval);
422 write_u8_inc(&wrptr, REG_DRAM_WAIT_ACK);
424 ret = sigma_write_sr(devc, buf, wrptr - buf);
428 return sigma_read_sr(devc, data, numchunks * ROW_LENGTH_BYTES);
431 /* Upload trigger look-up tables to Sigma. */
432 SR_PRIV int sigma_write_trigger_lut(struct dev_context *devc,
433 struct triggerlut *lut)
437 uint8_t m3d, m2d, m1d, m0d;
438 uint8_t buf[6], *wrptr;
440 uint16_t lutreg, selreg;
444 * Translate the LUT part of the trigger configuration from the
445 * application's perspective to the hardware register's bitfield
446 * layout. Send the LUT to the device. This configures the logic
447 * which combines pin levels or edges.
449 for (lut_addr = 0; lut_addr < 16; lut_addr++) {
461 /* M2D3 M2D2 M2D1 M2D0 */
463 if (lut->m2d[3] & bit)
465 if (lut->m2d[2] & bit)
467 if (lut->m2d[1] & bit)
469 if (lut->m2d[0] & bit)
472 /* M1D3 M1D2 M1D1 M1D0 */
474 if (lut->m1d[3] & bit)
476 if (lut->m1d[2] & bit)
478 if (lut->m1d[1] & bit)
480 if (lut->m1d[0] & bit)
483 /* M0D3 M0D2 M0D1 M0D0 */
485 if (lut->m0d[3] & bit)
487 if (lut->m0d[2] & bit)
489 if (lut->m0d[1] & bit)
491 if (lut->m0d[0] & bit)
495 * Send 16bits with M3D/M2D and M1D/M0D bit masks to the
496 * TriggerSelect register, then strobe the LUT write by
497 * passing A3-A0 to TriggerSelect2. Hold RESET during LUT
502 lutreg <<= 4; lutreg |= m3d;
503 lutreg <<= 4; lutreg |= m2d;
504 lutreg <<= 4; lutreg |= m1d;
505 lutreg <<= 4; lutreg |= m0d;
506 write_u16be_inc(&wrptr, lutreg);
507 ret = sigma_write_register(devc, WRITE_TRIGGER_SELECT,
511 trgsel2 = TRGSEL2_RESET | TRGSEL2_LUT_WRITE |
512 (lut_addr & TRGSEL2_LUT_ADDR_MASK);
513 ret = sigma_set_register(devc, WRITE_TRIGGER_SELECT2, trgsel2);
519 * Send the parameters. This covers counters and durations.
523 selreg |= (lut->params.selinc & TRGSEL_SELINC_MASK) << TRGSEL_SELINC_SHIFT;
524 selreg |= (lut->params.selres & TRGSEL_SELRES_MASK) << TRGSEL_SELRES_SHIFT;
525 selreg |= (lut->params.sela & TRGSEL_SELA_MASK) << TRGSEL_SELA_SHIFT;
526 selreg |= (lut->params.selb & TRGSEL_SELB_MASK) << TRGSEL_SELB_SHIFT;
527 selreg |= (lut->params.selc & TRGSEL_SELC_MASK) << TRGSEL_SELC_SHIFT;
528 selreg |= (lut->params.selpresc & TRGSEL_SELPRESC_MASK) << TRGSEL_SELPRESC_SHIFT;
529 write_u16be_inc(&wrptr, selreg);
530 write_u16be_inc(&wrptr, lut->params.cmpb);
531 write_u16be_inc(&wrptr, lut->params.cmpa);
532 ret = sigma_write_register(devc, WRITE_TRIGGER_SELECT, buf, wrptr - buf);
540 * See Xilinx UG332 for Spartan-3 FPGA configuration. The SIGMA device
541 * uses FTDI bitbang mode for netlist download in slave serial mode.
542 * (LATER: The OMEGA device's cable contains a more capable FTDI chip
543 * and uses MPSSE mode for bitbang. -- Can we also use FT232H in FT245
544 * compatible bitbang mode? For maximum code re-use and reduced libftdi
545 * dependency? See section 3.5.5 of FT232H: D0 clk, D1 data (out), D2
546 * data (in), D3 select, D4-7 GPIOL. See section 3.5.7 for MCU FIFO.)
548 * 750kbps rate (four times the speed of sigmalogan) works well for
549 * netlist download. All pins except INIT_B are output pins during
550 * configuration download.
552 * Some pins are inverted as a byproduct of level shifting circuitry.
553 * That's why high CCLK level (from the cable's point of view) is idle
554 * from the FPGA's perspective.
556 * The vendor's literature discusses a "suicide sequence" which ends
557 * regular FPGA execution and should be sent before entering bitbang
558 * mode and sending configuration data. Set D7 and toggle D2, D3, D4
561 #define BB_PIN_CCLK BIT(0) /* D0, CCLK */
562 #define BB_PIN_PROG BIT(1) /* D1, PROG */
563 #define BB_PIN_D2 BIT(2) /* D2, (part of) SUICIDE */
564 #define BB_PIN_D3 BIT(3) /* D3, (part of) SUICIDE */
565 #define BB_PIN_D4 BIT(4) /* D4, (part of) SUICIDE (unused?) */
566 #define BB_PIN_INIT BIT(5) /* D5, INIT, input pin */
567 #define BB_PIN_DIN BIT(6) /* D6, DIN */
568 #define BB_PIN_D7 BIT(7) /* D7, (part of) SUICIDE */
570 #define BB_BITRATE (750 * 1000)
571 #define BB_PINMASK (0xff & ~BB_PIN_INIT)
574 * Initiate slave serial mode for configuration download. Which is done
575 * by pulsing PROG_B and sensing INIT_B. Make sure CCLK is idle before
576 * initiating the configuration download.
578 * Run a "suicide sequence" first to terminate the regular FPGA operation
579 * before reconfiguration. The FTDI cable is single channel, and shares
580 * pins which are used for data communication in FIFO mode with pins that
581 * are used for FPGA configuration in bitbang mode. Hardware defaults for
582 * unconfigured hardware, and runtime conditions after FPGA configuration
583 * need to cooperate such that re-configuration of the FPGA can start.
585 static int sigma_fpga_init_bitbang_once(struct dev_context *devc)
587 const uint8_t suicide[] = {
588 BB_PIN_D7 | BB_PIN_D2,
589 BB_PIN_D7 | BB_PIN_D2,
590 BB_PIN_D7 | BB_PIN_D3,
591 BB_PIN_D7 | BB_PIN_D2,
592 BB_PIN_D7 | BB_PIN_D3,
593 BB_PIN_D7 | BB_PIN_D2,
594 BB_PIN_D7 | BB_PIN_D3,
595 BB_PIN_D7 | BB_PIN_D2,
597 const uint8_t init_array[] = {
599 BB_PIN_CCLK | BB_PIN_PROG,
600 BB_PIN_CCLK | BB_PIN_PROG,
613 /* Section 2. part 1), do the FPGA suicide. */
615 ret |= sigma_write_sr(devc, suicide, sizeof(suicide));
616 ret |= sigma_write_sr(devc, suicide, sizeof(suicide));
617 ret |= sigma_write_sr(devc, suicide, sizeof(suicide));
618 ret |= sigma_write_sr(devc, suicide, sizeof(suicide));
623 /* Section 2. part 2), pulse PROG. */
624 ret = sigma_write_sr(devc, init_array, sizeof(init_array));
628 ftdi_usb_purge_buffers(&devc->ftdi.ctx);
631 * Wait until the FPGA asserts INIT_B. Check in a maximum number
632 * of bursts with a given delay between them. Read as many pin
633 * capture results as the combination of FTDI chip and FTID lib
634 * may provide. Cope with absence of pin capture data in a cycle.
635 * This approach shall result in fast reponse in case of success,
636 * low cost of execution during wait, reliable error handling in
637 * the transport layer, and robust response to failure or absence
638 * of result data (hardware inactivity after stimulus).
643 ret = sigma_read_raw(devc, &data, sizeof(data));
646 if (ret == sizeof(data) && (data & BB_PIN_INIT))
648 } while (ret == sizeof(data));
653 return SR_ERR_TIMEOUT;
657 * This is belt and braces. Re-run the bitbang initiation sequence a few
658 * times should first attempts fail. Failure is rare but can happen (was
659 * observed during driver development).
661 static int sigma_fpga_init_bitbang(struct dev_context *devc)
668 ret = sigma_fpga_init_bitbang_once(devc);
671 if (ret != SR_ERR_TIMEOUT)
678 * Configure the FPGA for logic-analyzer mode.
680 static int sigma_fpga_init_la(struct dev_context *devc)
682 uint8_t buf[20], *wrptr;
683 uint8_t data_55, data_aa, mode;
685 const uint8_t *rdptr;
690 /* Read ID register. */
691 write_u8_inc(&wrptr, REG_ADDR_LOW | LO4(READ_ID));
692 write_u8_inc(&wrptr, REG_ADDR_HIGH | HI4(READ_ID));
693 write_u8_inc(&wrptr, REG_READ_ADDR);
695 /* Write 0x55 to scratch register, read back. */
697 write_u8_inc(&wrptr, REG_ADDR_LOW | LO4(WRITE_TEST));
698 write_u8_inc(&wrptr, REG_ADDR_HIGH | HI4(WRITE_TEST));
699 write_u8_inc(&wrptr, REG_DATA_LOW | LO4(data_55));
700 write_u8_inc(&wrptr, REG_DATA_HIGH_WRITE | HI4(data_55));
701 write_u8_inc(&wrptr, REG_READ_ADDR);
703 /* Write 0xaa to scratch register, read back. */
705 write_u8_inc(&wrptr, REG_ADDR_LOW | LO4(WRITE_TEST));
706 write_u8_inc(&wrptr, REG_ADDR_HIGH | HI4(WRITE_TEST));
707 write_u8_inc(&wrptr, REG_DATA_LOW | LO4(data_aa));
708 write_u8_inc(&wrptr, REG_DATA_HIGH_WRITE | HI4(data_aa));
709 write_u8_inc(&wrptr, REG_READ_ADDR);
711 /* Initiate SDRAM initialization in mode register. */
712 mode = WMR_SDRAMINIT;
713 write_u8_inc(&wrptr, REG_ADDR_LOW | LO4(WRITE_MODE));
714 write_u8_inc(&wrptr, REG_ADDR_HIGH | HI4(WRITE_MODE));
715 write_u8_inc(&wrptr, REG_DATA_LOW | LO4(mode));
716 write_u8_inc(&wrptr, REG_DATA_HIGH_WRITE | HI4(mode));
719 * Send the command sequence which contains 3 READ requests.
720 * Expect to see the corresponding 3 response bytes.
722 ret = sigma_write_sr(devc, buf, wrptr - buf);
724 sr_err("Could not request LA start response.");
727 ret = sigma_read_sr(devc, result, ARRAY_SIZE(result));
729 sr_err("Could not receive LA start response.");
733 if (read_u8_inc(&rdptr) != 0xa6) {
734 sr_err("Unexpected ID response.");
737 if (read_u8_inc(&rdptr) != data_55) {
738 sr_err("Unexpected scratch read-back (55).");
741 if (read_u8_inc(&rdptr) != data_aa) {
742 sr_err("Unexpected scratch read-back (aa).");
750 * Read the firmware from a file and transform it into a series of bitbang
751 * pulses used to program the FPGA. Note that the *bb_cmd must be free()'d
752 * by the caller of this function.
754 static int sigma_fw_2_bitbang(struct sr_context *ctx, const char *name,
755 uint8_t **bb_cmd, size_t *bb_cmd_size)
763 uint8_t *bb_stream, *bbs, byte, mask, v;
765 /* Retrieve the on-disk firmware file content. */
766 firmware = sr_resource_load(ctx, SR_RESOURCE_FIRMWARE, name,
767 &file_size, SIGMA_FIRMWARE_SIZE_LIMIT);
771 /* Unscramble the file content (XOR with "random" sequence). */
776 imm = (imm + 0xa853753) % 177 + (imm * 0x8034052);
781 * Generate a sequence of bitbang samples. With two samples per
782 * FPGA configuration bit, providing the level for the DIN signal
783 * as well as two edges for CCLK. See Xilinx UG332 for details
784 * ("slave serial" mode).
786 * Note that CCLK is inverted in hardware. That's why the
787 * respective bit is first set and then cleared in the bitbang
788 * sample sets. So that the DIN level will be stable when the
789 * data gets sampled at the rising CCLK edge, and the signals'
790 * setup time constraint will be met.
792 * The caller will put the FPGA into download mode, will send
793 * the bitbang samples, and release the allocated memory.
795 bb_size = file_size * 8 * 2;
796 bb_stream = g_try_malloc(bb_size);
798 sr_err("Memory allocation failed during firmware upload.");
800 return SR_ERR_MALLOC;
809 v = (byte & mask) ? BB_PIN_DIN : 0;
811 *bbs++ = v | BB_PIN_CCLK;
817 /* The transformation completed successfully, return the result. */
819 *bb_cmd_size = bb_size;
824 static int upload_firmware(struct sr_context *ctx, struct dev_context *devc,
825 enum sigma_firmware_idx firmware_idx)
831 const char *firmware;
833 /* Check for valid firmware file selection. */
834 if (firmware_idx >= ARRAY_SIZE(firmware_files))
836 firmware = firmware_files[firmware_idx];
837 if (!firmware || !*firmware)
840 /* Avoid downloading the same firmware multiple times. */
841 if (devc->firmware_idx == firmware_idx) {
842 sr_info("Not uploading firmware file '%s' again.", firmware);
846 devc->state = SIGMA_CONFIG;
848 /* Set the cable to bitbang mode. */
849 ret = ftdi_set_bitmode(&devc->ftdi.ctx, BB_PINMASK, BITMODE_BITBANG);
851 sr_err("Could not setup cable mode for upload: %s",
852 ftdi_get_error_string(&devc->ftdi.ctx));
855 ret = ftdi_set_baudrate(&devc->ftdi.ctx, BB_BITRATE);
857 sr_err("Could not setup bitrate for upload: %s",
858 ftdi_get_error_string(&devc->ftdi.ctx));
862 /* Initiate FPGA configuration mode. */
863 ret = sigma_fpga_init_bitbang(devc);
865 sr_err("Could not initiate firmware upload to hardware");
869 /* Prepare wire format of the firmware image. */
870 ret = sigma_fw_2_bitbang(ctx, firmware, &buf, &buf_size);
872 sr_err("Could not prepare file %s for upload.", firmware);
876 /* Write the FPGA netlist to the cable. */
877 sr_info("Uploading firmware file '%s'.", firmware);
878 ret = sigma_write_sr(devc, buf, buf_size);
881 sr_err("Could not upload firmware file '%s'.", firmware);
885 /* Leave bitbang mode and discard pending input data. */
886 ret = ftdi_set_bitmode(&devc->ftdi.ctx, 0, BITMODE_RESET);
888 sr_err("Could not setup cable mode after upload: %s",
889 ftdi_get_error_string(&devc->ftdi.ctx));
892 ftdi_usb_purge_buffers(&devc->ftdi.ctx);
893 while (sigma_read_raw(devc, &pins, sizeof(pins)) > 0)
896 /* Initialize the FPGA for logic-analyzer mode. */
897 ret = sigma_fpga_init_la(devc);
899 sr_err("Hardware response after firmware upload failed.");
903 /* Keep track of successful firmware download completion. */
904 devc->state = SIGMA_IDLE;
905 devc->firmware_idx = firmware_idx;
906 sr_info("Firmware uploaded.");
912 * The driver supports user specified time or sample count limits. The
913 * device's hardware supports neither, and hardware compression prevents
914 * reliable detection of "fill levels" (currently reached sample counts)
915 * from register values during acquisition. That's why the driver needs
916 * to apply some heuristics:
918 * - The (optional) sample count limit and the (normalized) samplerate
919 * get mapped to an estimated duration for these samples' acquisition.
920 * - The (optional) time limit gets checked as well. The lesser of the
921 * two limits will terminate the data acquisition phase. The exact
922 * sample count limit gets enforced in session feed submission paths.
923 * - Some slack needs to be given to account for hardware pipelines as
924 * well as late storage of last chunks after compression thresholds
925 * are tripped. The resulting data set will span at least the caller
926 * specified period of time, which shall be perfectly acceptable.
928 * With RLE compression active, up to 64K sample periods can pass before
929 * a cluster accumulates. Which translates to 327ms at 200kHz. Add two
930 * times that period for good measure, one is not enough to flush the
931 * hardware pipeline (observation from an earlier experiment).
933 SR_PRIV int sigma_set_acquire_timeout(struct dev_context *devc)
937 uint64_t user_count, user_msecs;
938 uint64_t worst_cluster_time_ms;
939 uint64_t count_msecs, acquire_msecs;
941 sr_sw_limits_init(&devc->limit.acquire);
942 devc->late_trigger_timeout = FALSE;
944 /* Get sample count limit, convert to msecs. */
945 ret = sr_sw_limits_config_get(&devc->limit.config,
946 SR_CONF_LIMIT_SAMPLES, &data);
949 user_count = g_variant_get_uint64(data);
950 g_variant_unref(data);
952 if (devc->use_triggers) {
953 user_count *= 100 - devc->capture_ratio;
957 count_msecs = 1000 * user_count / devc->clock.samplerate + 1;
959 /* Get time limit, which is in msecs. */
960 ret = sr_sw_limits_config_get(&devc->limit.config,
961 SR_CONF_LIMIT_MSEC, &data);
964 user_msecs = g_variant_get_uint64(data);
965 g_variant_unref(data);
966 if (devc->use_triggers) {
967 user_msecs *= 100 - devc->capture_ratio;
971 /* Get the lesser of them, with both being optional. */
972 acquire_msecs = ~UINT64_C(0);
973 if (user_count && count_msecs < acquire_msecs)
974 acquire_msecs = count_msecs;
975 if (user_msecs && user_msecs < acquire_msecs)
976 acquire_msecs = user_msecs;
977 if (acquire_msecs == ~UINT64_C(0))
980 /* Add some slack, and use that timeout for acquisition. */
981 worst_cluster_time_ms = 1000 * 65536 / devc->clock.samplerate;
982 acquire_msecs += 2 * worst_cluster_time_ms;
983 data = g_variant_new_uint64(acquire_msecs);
984 ret = sr_sw_limits_config_set(&devc->limit.acquire,
985 SR_CONF_LIMIT_MSEC, data);
986 g_variant_unref(data);
990 /* Deferred or immediate (trigger-less) timeout period start. */
991 if (devc->use_triggers)
992 devc->late_trigger_timeout = TRUE;
994 sr_sw_limits_acquisition_start(&devc->limit.acquire);
1000 * Check whether a caller specified samplerate matches the device's
1001 * hardware constraints (can be used for acquisition). Optionally yield
1002 * a value that approximates the original spec.
1004 * This routine assumes that input specs are in the 200kHz to 200MHz
1005 * range of supported rates, and callers typically want to normalize a
1006 * given value to the hardware capabilities. Values in the 50MHz range
1007 * get rounded up by default, to avoid a more expensive check for the
1008 * closest match, while higher sampling rate is always desirable during
1009 * measurement. Input specs which exactly match hardware capabilities
1010 * remain unaffected. Because 100/200MHz rates also limit the number of
1011 * available channels, they are not suggested by this routine, instead
1012 * callers need to pick them consciously.
1014 SR_PRIV int sigma_normalize_samplerate(uint64_t want_rate, uint64_t *have_rate)
1018 /* Accept exact matches for 100/200MHz. */
1019 if (want_rate == SR_MHZ(200) || want_rate == SR_MHZ(100)) {
1021 *have_rate = want_rate;
1025 /* Accept 200kHz to 50MHz range, and map to near value. */
1026 if (want_rate >= SR_KHZ(200) && want_rate <= SR_MHZ(50)) {
1027 div = SR_MHZ(50) / want_rate;
1028 rate = SR_MHZ(50) / div;
1037 /* Gets called at probe time. Can seed software settings from hardware state. */
1038 SR_PRIV int sigma_fetch_hw_config(const struct sr_dev_inst *sdi)
1040 struct dev_context *devc;
1042 uint8_t regaddr, regval;
1048 /* Seed configuration values from defaults. */
1049 devc->firmware_idx = SIGMA_FW_NONE;
1050 devc->clock.samplerate = samplerates[0];
1053 * Ideally the device driver could retrieve recently stored
1054 * details from hardware registers, thus re-use user specified
1055 * configuration values across sigrok sessions. Which could
1056 * avoid repeated expensive though unnecessary firmware uploads,
1057 * improve performance and usability. Unfortunately it appears
1058 * that the registers range which is documented as available for
1059 * application use keeps providing 0xff data content. At least
1060 * with the netlist version which ships with sigrok. The same
1061 * was observed with unused registers in the first page.
1065 /* This is for research, currently does not work yet. */
1066 ret = sigma_check_open(sdi);
1069 ret = sigma_set_register(devc, regaddr, 'F');
1070 ret = sigma_get_register(devc, regaddr, ®val);
1071 sr_warn("%s() reg[%u] val[%u] rc[%d]", __func__, regaddr, regval, ret);
1072 ret = sigma_check_close(devc);
1076 /* Gets called after successful (volatile) hardware configuration. */
1077 SR_PRIV int sigma_store_hw_config(const struct sr_dev_inst *sdi)
1079 /* TODO See above, registers seem to not hold written data. */
1084 SR_PRIV int sigma_set_samplerate(const struct sr_dev_inst *sdi)
1086 struct dev_context *devc;
1087 struct drv_context *drvc;
1088 uint64_t samplerate;
1090 size_t num_channels;
1093 drvc = sdi->driver->context;
1095 /* Accept any caller specified rate which the hardware supports. */
1096 ret = sigma_normalize_samplerate(devc->clock.samplerate, &samplerate);
1101 * Depending on the samplerates of 200/100/50- MHz, specific
1102 * firmware is required and higher rates might limit the set
1103 * of available channels.
1105 num_channels = devc->interp.num_channels;
1106 if (samplerate <= SR_MHZ(50)) {
1107 ret = upload_firmware(drvc->sr_ctx, devc, SIGMA_FW_50MHZ);
1109 } else if (samplerate == SR_MHZ(100)) {
1110 ret = upload_firmware(drvc->sr_ctx, devc, SIGMA_FW_100MHZ);
1112 } else if (samplerate == SR_MHZ(200)) {
1113 ret = upload_firmware(drvc->sr_ctx, devc, SIGMA_FW_200MHZ);
1118 * The samplerate affects the number of available logic channels
1119 * as well as a sample memory layout detail (the number of samples
1120 * which the device will communicate within an "event").
1123 devc->interp.num_channels = num_channels;
1124 devc->interp.samples_per_event = 16 / devc->interp.num_channels;
1128 * Store the firmware type and most recently configured samplerate
1129 * in hardware, such that subsequent sessions can start from there.
1130 * This is a "best effort" approach. Failure is non-fatal.
1133 (void)sigma_store_hw_config(sdi);
1139 * Arrange for a session feed submit buffer. A queue where a number of
1140 * samples gets accumulated to reduce the number of send calls. Which
1141 * also enforces an optional sample count limit for data acquisition.
1143 * The buffer holds up to CHUNK_SIZE bytes. The unit size is fixed (the
1144 * driver provides a fixed channel layout regardless of samplerate).
1147 #define CHUNK_SIZE (4 * 1024 * 1024)
1149 struct submit_buffer {
1151 size_t max_samples, curr_samples;
1152 uint8_t *sample_data;
1153 uint8_t *write_pointer;
1154 struct sr_dev_inst *sdi;
1155 struct sr_datafeed_packet packet;
1156 struct sr_datafeed_logic logic;
1159 static int alloc_submit_buffer(struct sr_dev_inst *sdi)
1161 struct dev_context *devc;
1162 struct submit_buffer *buffer;
1167 buffer = g_malloc0(sizeof(*buffer));
1168 devc->buffer = buffer;
1170 buffer->unit_size = sizeof(uint16_t);
1172 size /= buffer->unit_size;
1173 buffer->max_samples = size;
1174 size *= buffer->unit_size;
1175 buffer->sample_data = g_try_malloc0(size);
1176 if (!buffer->sample_data)
1177 return SR_ERR_MALLOC;
1178 buffer->write_pointer = buffer->sample_data;
1179 sr_sw_limits_init(&devc->limit.submit);
1182 memset(&buffer->logic, 0, sizeof(buffer->logic));
1183 buffer->logic.unitsize = buffer->unit_size;
1184 buffer->logic.data = buffer->sample_data;
1185 memset(&buffer->packet, 0, sizeof(buffer->packet));
1186 buffer->packet.type = SR_DF_LOGIC;
1187 buffer->packet.payload = &buffer->logic;
1192 static int setup_submit_limit(struct dev_context *devc)
1194 struct sr_sw_limits *limits;
1199 limits = &devc->limit.submit;
1201 ret = sr_sw_limits_config_get(&devc->limit.config,
1202 SR_CONF_LIMIT_SAMPLES, &data);
1205 total = g_variant_get_uint64(data);
1206 g_variant_unref(data);
1208 sr_sw_limits_init(limits);
1210 data = g_variant_new_uint64(total);
1211 ret = sr_sw_limits_config_set(limits,
1212 SR_CONF_LIMIT_SAMPLES, data);
1213 g_variant_unref(data);
1218 sr_sw_limits_acquisition_start(limits);
1223 static void free_submit_buffer(struct dev_context *devc)
1225 struct submit_buffer *buffer;
1230 buffer = devc->buffer;
1233 devc->buffer = NULL;
1235 g_free(buffer->sample_data);
1239 static int flush_submit_buffer(struct dev_context *devc)
1241 struct submit_buffer *buffer;
1244 buffer = devc->buffer;
1246 /* Is queued sample data available? */
1247 if (!buffer->curr_samples)
1250 /* Submit to the session feed. */
1251 buffer->logic.length = buffer->curr_samples * buffer->unit_size;
1252 ret = sr_session_send(buffer->sdi, &buffer->packet);
1256 /* Rewind queue position. */
1257 buffer->curr_samples = 0;
1258 buffer->write_pointer = buffer->sample_data;
1263 static int addto_submit_buffer(struct dev_context *devc,
1264 uint16_t sample, size_t count)
1266 struct submit_buffer *buffer;
1267 struct sr_sw_limits *limits;
1270 buffer = devc->buffer;
1271 limits = &devc->limit.submit;
1272 if (!devc->use_triggers && sr_sw_limits_check(limits))
1276 * Individually accumulate and check each sample, such that
1277 * accumulation between flushes won't exceed local storage, and
1278 * enforcement of user specified limits is exact.
1281 write_u16le_inc(&buffer->write_pointer, sample);
1282 buffer->curr_samples++;
1283 if (buffer->curr_samples == buffer->max_samples) {
1284 ret = flush_submit_buffer(devc);
1288 sr_sw_limits_update_samples_read(limits, 1);
1289 if (!devc->use_triggers && sr_sw_limits_check(limits))
1296 static void sigma_location_break_down(struct sigma_location *loc)
1299 loc->line = loc->raw / ROW_LENGTH_U16;
1300 loc->line += ROW_COUNT;
1301 loc->line %= ROW_COUNT;
1302 loc->cluster = loc->raw % ROW_LENGTH_U16;
1303 loc->event = loc->cluster % EVENTS_PER_CLUSTER;
1304 loc->cluster = loc->cluster / EVENTS_PER_CLUSTER;
1307 static gboolean sigma_location_is_eq(struct sigma_location *loc1,
1308 struct sigma_location *loc2, gboolean with_event)
1314 if (loc1->line != loc2->line)
1316 if (loc1->cluster != loc2->cluster)
1319 if (with_event && loc1->event != loc2->event)
1325 /* Decrement the broken-down location fields (leave 'raw' as is). */
1326 static void sigma_location_decrement(struct sigma_location *loc,
1327 gboolean with_event)
1336 loc->event = EVENTS_PER_CLUSTER - 1;
1341 loc->cluster = CLUSTERS_PER_ROW - 1;
1345 loc->line = ROW_COUNT - 1;
1348 static void sigma_location_increment(struct sigma_location *loc)
1354 if (++loc->event < EVENTS_PER_CLUSTER)
1357 if (++loc->cluster < CLUSTERS_PER_ROW)
1360 if (++loc->line < ROW_COUNT)
1366 * Determine the position where to open the period of trigger match
1367 * checks. Setup an "impossible" location when triggers are not used.
1368 * Start from the hardware provided 'trig' position otherwise, and
1369 * go back a few clusters, but don't go before the 'start' position.
1371 static void rewind_trig_arm_pos(struct dev_context *devc, size_t count)
1373 struct sigma_sample_interp *interp;
1377 interp = &devc->interp;
1379 if (!devc->use_triggers) {
1380 interp->trig_arm.raw = ~0;
1381 sigma_location_break_down(&interp->trig_arm);
1385 interp->trig_arm = interp->trig;
1387 if (sigma_location_is_eq(&interp->trig_arm, &interp->start, TRUE))
1389 sigma_location_decrement(&interp->trig_arm, TRUE);
1393 static int alloc_sample_buffer(struct dev_context *devc,
1394 size_t stop_pos, size_t trig_pos, uint8_t mode)
1396 struct sigma_sample_interp *interp;
1400 interp = &devc->interp;
1403 * Either fetch sample memory from absolute start of DRAM to the
1404 * current write position. Or from after the current write position
1405 * to before the current write position, if the write pointer has
1406 * wrapped around at the upper DRAM boundary. Assume that the line
1407 * which most recently got written to is of unknown state, ignore
1408 * its content in the "wrapped" case.
1410 wrapped = mode & RMR_ROUND;
1411 interp->start.raw = 0;
1412 interp->stop.raw = stop_pos;
1414 interp->start.raw = stop_pos;
1415 interp->start.raw >>= ROW_SHIFT;
1416 interp->start.raw++;
1417 interp->start.raw <<= ROW_SHIFT;
1418 interp->stop.raw = stop_pos;
1419 interp->stop.raw >>= ROW_SHIFT;
1421 interp->stop.raw <<= ROW_SHIFT;
1423 interp->trig.raw = trig_pos;
1424 interp->iter.raw = 0;
1426 /* Break down raw values to line, cluster, event fields. */
1427 sigma_location_break_down(&interp->start);
1428 sigma_location_break_down(&interp->stop);
1429 sigma_location_break_down(&interp->trig);
1430 sigma_location_break_down(&interp->iter);
1433 * The hardware provided trigger location "is late" because of
1434 * latency in hardware pipelines. It points to after the trigger
1435 * condition match. Arrange for a software check of sample data
1436 * matches starting just a little before the hardware provided
1437 * location. The "4 clusters" distance is an arbitrary choice.
1439 rewind_trig_arm_pos(devc, 4 * EVENTS_PER_CLUSTER);
1440 memset(&interp->trig_chk, 0, sizeof(interp->trig_chk));
1442 /* Determine which DRAM lines to fetch from the device. */
1443 memset(&interp->fetch, 0, sizeof(interp->fetch));
1444 interp->fetch.lines_total = interp->stop.line + 1;
1445 interp->fetch.lines_total -= interp->start.line;
1446 interp->fetch.lines_total += ROW_COUNT;
1447 interp->fetch.lines_total %= ROW_COUNT;
1448 interp->fetch.lines_done = 0;
1450 /* Arrange for chunked download, N lines per USB request. */
1451 interp->fetch.lines_per_read = 32;
1452 alloc_size = sizeof(devc->interp.fetch.rcvd_lines[0]);
1453 alloc_size *= devc->interp.fetch.lines_per_read;
1454 devc->interp.fetch.rcvd_lines = g_try_malloc0(alloc_size);
1455 if (!devc->interp.fetch.rcvd_lines)
1456 return SR_ERR_MALLOC;
1461 static uint16_t sigma_deinterlace_data_4x4(uint16_t indata, int idx);
1462 static uint16_t sigma_deinterlace_data_2x8(uint16_t indata, int idx);
1464 static int fetch_sample_buffer(struct dev_context *devc)
1466 struct sigma_sample_interp *interp;
1469 const uint8_t *rdptr;
1472 interp = &devc->interp;
1474 /* First invocation? Seed the iteration position. */
1475 if (!interp->fetch.lines_done) {
1476 interp->iter = interp->start;
1479 /* Get another set of DRAM lines in one read call. */
1480 count = interp->fetch.lines_total - interp->fetch.lines_done;
1481 if (count > interp->fetch.lines_per_read)
1482 count = interp->fetch.lines_per_read;
1483 ret = sigma_read_dram(devc, interp->iter.line, count,
1484 (uint8_t *)interp->fetch.rcvd_lines);
1487 interp->fetch.lines_rcvd = count;
1488 interp->fetch.curr_line = &interp->fetch.rcvd_lines[0];
1490 /* First invocation? Get initial timestamp and sample data. */
1491 if (!interp->fetch.lines_done) {
1492 rdptr = (void *)interp->fetch.curr_line;
1493 ts = read_u16le_inc(&rdptr);
1494 data = read_u16le_inc(&rdptr);
1495 if (interp->samples_per_event == 4) {
1496 data = sigma_deinterlace_data_4x4(data, 0);
1497 } else if (interp->samples_per_event == 2) {
1498 data = sigma_deinterlace_data_2x8(data, 0);
1500 interp->last.ts = ts;
1501 interp->last.sample = data;
1507 static void free_sample_buffer(struct dev_context *devc)
1509 g_free(devc->interp.fetch.rcvd_lines);
1510 devc->interp.fetch.rcvd_lines = NULL;
1511 devc->interp.fetch.lines_per_read = 0;
1515 * Parse application provided trigger conditions to the driver's internal
1516 * presentation. Yields a mask of pins of interest, and their expected
1517 * pin levels or edges.
1519 * In 100 and 200 MHz mode, only a single pin's rising/falling edge can be
1520 * set as trigger. In 50- MHz modes, two rising/falling edges can be set,
1521 * in addition to value/mask specs for any number of channels.
1523 * Hardware implementation detail: When more than one edge is specified,
1524 * then the condition is only considered a match when _all_ transitions
1525 * are seen in the same 20ns check interval, regardless of the user's
1526 * perceived samplerate which can be a fraction of 50MHz. Which reduces
1527 * practical use to edges on a single pin in addition to data patterns.
1528 * Which still covers a lot of users' typical scenarios. Not an issue,
1529 * just something to remain aware of.
1531 * The Sigma hardware also supports complex triggers which involve the
1532 * logical combination of several patterns, pulse durations, counts of
1533 * condition matches, A-then-B sequences, etc. But this has not been
1534 * implemented yet here, and applications may lack means to express
1535 * these conditions (present the complex conditions to users for entry
1536 * and review, pass application specs to drivers covering the versatile
1539 * Implementor's note: This routine currently exclusively accepts input
1540 * in the form of sr_trigger stages, which results from "01rf-" choices
1541 * on a multitude of individual GUI traces, or the CLI's --trigger spec
1542 * which takes one list of <pin>=<value/edge> details.
1544 * TODO Consider the addition of SR_CONF_TRIGGER_PATTERN support, which
1545 * accepts a single free form string argument, and could describe a
1546 * multi-bit pattern without the tedious trace name/index selection.
1547 * Fortunately the number of channels is fixed for this device, we need
1548 * not come up with variable length support and counts beyond 64. _When_
1549 * --trigger as well as SR_CONF_TRIGGER_PATTERN are supported, then the
1550 * implementation needs to come up with priorities for these sources of
1551 * input specs, or enforce exclusive use of either form (at one time,
1552 * per acquisition / invocation).
1554 * Text forms that may be worth supporting:
1555 * - Simple forms, mere numbers, optional base specs. These are easiest
1556 * to implement with existing common conversion helpers.
1557 * triggerpattern=<value>[/<mask>]
1558 * triggerpattern=255
1559 * triggerpattern=45054
1560 * triggerpattern=0xaffe
1561 * triggerpattern=0xa0f0/0xf0f0
1562 * triggerpattern=0b1010111111111110/0x7ffe
1563 * - Alternative bit pattern form, including wildcards in a single value.
1564 * This cannot use common conversion support, needs special handling.
1565 * triggerpattern=0b1010xxxx1111xxx0
1566 * This is most similar to SR_CONF_TRIGGER_PATTERN as hameg-hmo uses
1567 * it. Passes the app's spec via SCPI to the device. See section 2.3.5
1568 * "Pattern trigger" and :TRIG:A:PATT:SOUR in the Hameg document.
1569 * - Prefixed form to tell the above variants apart, and support both of
1570 * them at the same time. Additional optional separator for long digit
1571 * runs, and edge support in the form which lists individual bits (not
1572 * useful for dec/hex formats).
1573 * triggerpattern=value=45054
1574 * triggerpattern=value=0b1010111111111110
1575 * triggerpattern=value=0xa0f0,mask=0xf0f0
1576 * triggerpattern=bits=1010-xxxx-1111-xxxx
1577 * triggerpattern=bits=0010-r100
1579 * TODO Check this set of processing rules for completeness/correctness.
1580 * - Do implement the prefixed format which covers most use cases, _and_
1581 * should be usable from CLI and GUI environments.
1582 * - Default to 'bits=' prefix if none was found (and only accept one
1583 * single key/value pair in that case with the default key).
1584 * - Accept dash and space separators in the 'bits=' value. Stick with
1585 * mere unseparated values for value and mask, use common conversion.
1586 * This results in transparent dec/bin/oct/hex support. Underscores?
1587 * - Accept 0/1 binary digits in 'bits=', as well as r/f/e edge specs.
1588 * - Only use --trigger (struct sr_trigger) when SR_CONF_TRIGGER_PATTERN
1589 * is absent? Or always accept --trigger in addition to the data pattern
1590 * spec? Then only accept edge specs from --trigger, since data pattern
1591 * was most importantly motivated by address/data bus inspection?
1592 * - TODO Consider edge=<pin><slope> as an optional additional spec in
1593 * the value= and mask= group? Does that help make exclusive support
1594 * for either --trigger or -c triggerpattern acceptable?
1595 * triggerpattern=value=0xa0f0,mask=0xb0f0,edge=15r
1596 * triggerpattern=bits=1r10-xxxx-1111-xxxx
1597 * triggerpattern=1r10-xxxx-1111-xxxx
1598 * - *Any* input spec regardless of format and origin must end up in the
1599 * 'struct sigma_trigger' internal presentation used by this driver.
1600 * It's desirable to have sigma_convert_trigger() do all the parsing,
1601 * and constraint checking in a central location.
1603 SR_PRIV int sigma_convert_trigger(const struct sr_dev_inst *sdi)
1605 struct dev_context *devc;
1606 struct sr_trigger *trigger;
1607 struct sr_trigger_stage *stage;
1608 struct sr_trigger_match *match;
1609 const GSList *l, *m;
1610 uint16_t channelbit;
1614 memset(&devc->trigger, 0, sizeof(devc->trigger));
1615 devc->use_triggers = FALSE;
1617 /* TODO Consider additional SR_CONF_TRIGGER_PATTERN support. */
1618 trigger = sr_session_trigger_get(sdi->session);
1623 for (l = trigger->stages; l; l = l->next) {
1625 for (m = stage->matches; m; m = m->next) {
1627 /* Ignore disabled channels with a trigger. */
1628 if (!match->channel->enabled)
1630 channelbit = BIT(match->channel->index);
1631 if (devc->clock.samplerate >= SR_MHZ(100)) {
1632 /* Fast trigger support. */
1633 if (edge_count > 0) {
1634 sr_err("100/200MHz modes limited to single trigger pin.");
1637 if (match->match == SR_TRIGGER_FALLING) {
1638 devc->trigger.fallingmask |= channelbit;
1639 } else if (match->match == SR_TRIGGER_RISING) {
1640 devc->trigger.risingmask |= channelbit;
1642 sr_err("100/200MHz modes limited to edge trigger.");
1648 /* Simple trigger support (event). */
1649 if (match->match == SR_TRIGGER_ONE) {
1650 devc->trigger.simplevalue |= channelbit;
1651 devc->trigger.simplemask |= channelbit;
1652 } else if (match->match == SR_TRIGGER_ZERO) {
1653 devc->trigger.simplevalue &= ~channelbit;
1654 devc->trigger.simplemask |= channelbit;
1655 } else if (match->match == SR_TRIGGER_FALLING) {
1656 devc->trigger.fallingmask |= channelbit;
1658 } else if (match->match == SR_TRIGGER_RISING) {
1659 devc->trigger.risingmask |= channelbit;
1664 * Actually, Sigma supports 2 rising/falling triggers,
1665 * but they are ORed and the current trigger syntax
1666 * does not permit ORed triggers.
1668 if (edge_count > 1) {
1669 sr_err("Limited to 1 edge trigger.");
1676 /* Keep track whether triggers are involved during acquisition. */
1677 devc->use_triggers = TRUE;
1682 static gboolean sample_matches_trigger(struct dev_context *devc, uint16_t sample)
1684 struct sigma_sample_interp *interp;
1685 uint16_t last_sample;
1686 struct sigma_trigger *t;
1687 gboolean simple_match, rising_match, falling_match;
1691 * This logic is about improving the precision of the hardware
1692 * provided trigger match position. Software checks are only
1693 * required for a short range of samples, and only when a user
1694 * specified trigger condition was involved during acquisition.
1698 if (!devc->use_triggers)
1700 interp = &devc->interp;
1701 if (!interp->trig_chk.armed)
1705 * Check if the current sample and its most recent transition
1706 * match the initially provided trigger condition. The data
1707 * must not fail either of the individual checks. Unused
1708 * trigger features remain neutral in the summary expression.
1710 last_sample = interp->last.sample;
1712 simple_match = (sample & t->simplemask) == t->simplevalue;
1713 rising_match = ((last_sample & t->risingmask) == 0) &&
1714 ((sample & t->risingmask) == t->risingmask);
1715 falling_match = ((last_sample & t->fallingmask) == t->fallingmask) &&
1716 ((sample & t->fallingmask) == 0);
1717 matched = simple_match && rising_match && falling_match;
1722 static int send_trigger_marker(struct dev_context *devc)
1726 ret = flush_submit_buffer(devc);
1729 ret = std_session_send_df_trigger(devc->buffer->sdi);
1736 static int check_and_submit_sample(struct dev_context *devc,
1737 uint16_t sample, size_t count)
1742 triggered = sample_matches_trigger(devc, sample);
1744 send_trigger_marker(devc);
1745 devc->interp.trig_chk.matched = TRUE;
1748 ret = addto_submit_buffer(devc, sample, count);
1755 static void sigma_location_check(struct dev_context *devc)
1757 struct sigma_sample_interp *interp;
1761 interp = &devc->interp;
1764 * Manage the period of trigger match checks in software.
1765 * Start supervision somewhere before the hardware provided
1766 * location. Stop supervision after an arbitrary amount of
1767 * event slots, or when a match was found.
1769 if (interp->trig_chk.armed) {
1770 interp->trig_chk.evt_remain--;
1771 if (!interp->trig_chk.evt_remain || interp->trig_chk.matched)
1772 interp->trig_chk.armed = FALSE;
1774 if (!interp->trig_chk.armed && !interp->trig_chk.matched) {
1775 if (sigma_location_is_eq(&interp->iter, &interp->trig_arm, TRUE)) {
1776 interp->trig_chk.armed = TRUE;
1777 interp->trig_chk.matched = FALSE;
1778 interp->trig_chk.evt_remain = 8 * EVENTS_PER_CLUSTER;
1783 * Force a trigger marker when the software check found no match
1784 * yet while the hardware provided position was reached. This
1785 * very probably is a user initiated button press.
1787 if (interp->trig_chk.armed) {
1788 if (sigma_location_is_eq(&interp->iter, &interp->trig, TRUE)) {
1789 (void)send_trigger_marker(devc);
1790 interp->trig_chk.matched = TRUE;
1796 * Return the timestamp of "DRAM cluster".
1798 static uint16_t sigma_dram_cluster_ts(struct sigma_dram_cluster *cluster)
1800 return read_u16le((const uint8_t *)&cluster->timestamp);
1804 * Return one 16bit data entity of a DRAM cluster at the specified index.
1806 static uint16_t sigma_dram_cluster_data(struct sigma_dram_cluster *cl, int idx)
1808 return read_u16le((const uint8_t *)&cl->samples[idx]);
1812 * Deinterlace sample data that was retrieved at 100MHz samplerate.
1813 * One 16bit item contains two samples of 8bits each. The bits of
1814 * multiple samples are interleaved.
1816 static uint16_t sigma_deinterlace_data_2x8(uint16_t indata, int idx)
1822 outdata |= (indata >> (0 * 2 - 0)) & (1 << 0);
1823 outdata |= (indata >> (1 * 2 - 1)) & (1 << 1);
1824 outdata |= (indata >> (2 * 2 - 2)) & (1 << 2);
1825 outdata |= (indata >> (3 * 2 - 3)) & (1 << 3);
1826 outdata |= (indata >> (4 * 2 - 4)) & (1 << 4);
1827 outdata |= (indata >> (5 * 2 - 5)) & (1 << 5);
1828 outdata |= (indata >> (6 * 2 - 6)) & (1 << 6);
1829 outdata |= (indata >> (7 * 2 - 7)) & (1 << 7);
1834 * Deinterlace sample data that was retrieved at 200MHz samplerate.
1835 * One 16bit item contains four samples of 4bits each. The bits of
1836 * multiple samples are interleaved.
1838 static uint16_t sigma_deinterlace_data_4x4(uint16_t indata, int idx)
1844 outdata |= (indata >> (0 * 4 - 0)) & (1 << 0);
1845 outdata |= (indata >> (1 * 4 - 1)) & (1 << 1);
1846 outdata |= (indata >> (2 * 4 - 2)) & (1 << 2);
1847 outdata |= (indata >> (3 * 4 - 3)) & (1 << 3);
1851 static void sigma_decode_dram_cluster(struct dev_context *devc,
1852 struct sigma_dram_cluster *dram_cluster,
1853 size_t events_in_cluster)
1855 uint16_t tsdiff, ts, sample, item16;
1860 * If this cluster is not adjacent to the previously received
1861 * cluster, then send the appropriate number of samples with the
1862 * previous values to the sigrok session. This "decodes RLE".
1864 * These samples cannot match the trigger since they just repeat
1865 * the previously submitted data pattern. (This assumption holds
1866 * for simple level and edge triggers. It would not for timed or
1867 * counted conditions, which currently are not supported.)
1869 ts = sigma_dram_cluster_ts(dram_cluster);
1870 tsdiff = ts - devc->interp.last.ts;
1872 sample = devc->interp.last.sample;
1873 count = tsdiff * devc->interp.samples_per_event;
1874 (void)check_and_submit_sample(devc, sample, count);
1876 devc->interp.last.ts = ts + EVENTS_PER_CLUSTER;
1879 * Grab sample data from the current cluster and prepare their
1880 * submission to the session feed. Handle samplerate dependent
1881 * memory layout of sample data. Accumulation of data chunks
1882 * before submission is transparent to this code path, specific
1883 * buffer depth is neither assumed nor required here.
1886 for (evt = 0; evt < events_in_cluster; evt++) {
1887 item16 = sigma_dram_cluster_data(dram_cluster, evt);
1888 if (devc->interp.samples_per_event == 4) {
1889 sample = sigma_deinterlace_data_4x4(item16, 0);
1890 check_and_submit_sample(devc, sample, 1);
1891 devc->interp.last.sample = sample;
1892 sample = sigma_deinterlace_data_4x4(item16, 1);
1893 check_and_submit_sample(devc, sample, 1);
1894 devc->interp.last.sample = sample;
1895 sample = sigma_deinterlace_data_4x4(item16, 2);
1896 check_and_submit_sample(devc, sample, 1);
1897 devc->interp.last.sample = sample;
1898 sample = sigma_deinterlace_data_4x4(item16, 3);
1899 check_and_submit_sample(devc, sample, 1);
1900 devc->interp.last.sample = sample;
1901 } else if (devc->interp.samples_per_event == 2) {
1902 sample = sigma_deinterlace_data_2x8(item16, 0);
1903 check_and_submit_sample(devc, sample, 1);
1904 devc->interp.last.sample = sample;
1905 sample = sigma_deinterlace_data_2x8(item16, 1);
1906 check_and_submit_sample(devc, sample, 1);
1907 devc->interp.last.sample = sample;
1910 check_and_submit_sample(devc, sample, 1);
1911 devc->interp.last.sample = sample;
1913 sigma_location_increment(&devc->interp.iter);
1914 sigma_location_check(devc);
1919 * Decode chunk of 1024 bytes, 64 clusters, 7 events per cluster.
1920 * Each event is 20ns apart, and can contain multiple samples.
1922 * For 200 MHz, events contain 4 samples for each channel, spread 5 ns apart.
1923 * For 100 MHz, events contain 2 samples for each channel, spread 10 ns apart.
1924 * For 50 MHz and below, events contain one sample for each channel,
1925 * spread 20 ns apart.
1927 static int decode_chunk_ts(struct dev_context *devc,
1928 struct sigma_dram_line *dram_line,
1929 size_t events_in_line)
1931 struct sigma_dram_cluster *dram_cluster;
1932 size_t clusters_in_line;
1933 size_t events_in_cluster;
1936 clusters_in_line = events_in_line;
1937 clusters_in_line += EVENTS_PER_CLUSTER - 1;
1938 clusters_in_line /= EVENTS_PER_CLUSTER;
1940 /* For each full DRAM cluster. */
1941 for (cluster = 0; cluster < clusters_in_line; cluster++) {
1942 dram_cluster = &dram_line->cluster[cluster];
1944 /* The last cluster might not be full. */
1945 if ((cluster == clusters_in_line - 1) &&
1946 (events_in_line % EVENTS_PER_CLUSTER)) {
1947 events_in_cluster = events_in_line % EVENTS_PER_CLUSTER;
1949 events_in_cluster = EVENTS_PER_CLUSTER;
1952 sigma_decode_dram_cluster(devc, dram_cluster,
1959 static int download_capture(struct sr_dev_inst *sdi)
1961 struct dev_context *devc;
1962 struct sigma_sample_interp *interp;
1963 uint32_t stoppos, triggerpos;
1966 size_t chunks_per_receive_call;
1969 interp = &devc->interp;
1972 * Check the mode register. Force stop the current acquisition
1973 * if it has not yet terminated before. Will block until the
1974 * acquisition stops, assuming that this won't take long. Should
1975 * execute exactly once, then keep finding its condition met.
1977 * Ask the hardware to stop data acquisition. Reception of the
1978 * FORCESTOP request makes the hardware "disable RLE" (store
1979 * clusters to DRAM regardless of whether pin state changes) and
1980 * raise the POSTTRIGGERED flag.
1982 ret = sigma_get_register(devc, READ_MODE, &modestatus);
1984 sr_err("Could not determine current device state.");
1987 if (!(modestatus & RMR_POSTTRIGGERED)) {
1988 sr_info("Downloading sample data.");
1989 devc->state = SIGMA_DOWNLOAD;
1991 modestatus = WMR_FORCESTOP | WMR_SDRAMWRITEEN;
1992 ret = sigma_set_register(devc, WRITE_MODE, modestatus);
1996 ret = sigma_get_register(devc, READ_MODE, &modestatus);
1998 sr_err("Could not poll for post-trigger state.");
2001 } while (!(modestatus & RMR_POSTTRIGGERED));
2005 * Switch the hardware from DRAM write (data acquisition) to
2006 * DRAM read (sample memory download). Prepare resources for
2007 * sample memory content retrieval. Should execute exactly once,
2008 * then keep finding its condition met.
2010 * Get the current positions (acquisition write pointer, and
2011 * trigger match location). With disabled triggers, use a value
2012 * for the location that will never match during interpretation.
2013 * Determine which area of the sample memory to retrieve,
2014 * allocate a receive buffer, and setup counters/pointers.
2016 if (!interp->fetch.lines_per_read) {
2017 ret = sigma_set_register(devc, WRITE_MODE, WMR_SDRAMREADEN);
2021 ret = sigma_read_pos(devc, &stoppos, &triggerpos, &modestatus);
2023 sr_err("Could not query capture positions/state.");
2026 if (!devc->use_triggers)
2028 if (!(modestatus & RMR_TRIGGERED))
2031 ret = alloc_sample_buffer(devc, stoppos, triggerpos, modestatus);
2035 ret = alloc_submit_buffer(sdi);
2038 ret = setup_submit_limit(devc);
2044 * Get another set of sample memory rows, and interpret its
2045 * content. Will execute as many times as it takes to complete
2046 * the memory region that the recent acquisition spans.
2048 * The size of a receive call's workload and the main loop's
2049 * receive call poll period determine the UI responsiveness and
2050 * the overall transfer time for the sample memory content.
2052 chunks_per_receive_call = 50;
2053 while (interp->fetch.lines_done < interp->fetch.lines_total) {
2054 size_t dl_events_in_line;
2056 /* Read another chunk of sample memory (several lines). */
2057 ret = fetch_sample_buffer(devc);
2061 /* Process lines of sample data. Last line may be short. */
2062 while (interp->fetch.lines_rcvd--) {
2063 dl_events_in_line = EVENTS_PER_ROW;
2064 if (interp->iter.line == interp->stop.line) {
2065 dl_events_in_line = interp->stop.raw & ROW_MASK;
2067 decode_chunk_ts(devc, interp->fetch.curr_line,
2069 interp->fetch.curr_line++;
2070 interp->fetch.lines_done++;
2073 /* Keep returning to application code for large data sets. */
2074 if (!--chunks_per_receive_call) {
2075 ret = flush_submit_buffer(devc);
2083 * Release previously allocated resources, and adjust state when
2084 * all of the sample memory was retrieved, and interpretation has
2085 * completed. Should execute exactly once.
2087 if (interp->fetch.lines_done >= interp->fetch.lines_total) {
2088 ret = flush_submit_buffer(devc);
2091 free_submit_buffer(devc);
2092 free_sample_buffer(devc);
2094 ret = std_session_send_df_end(sdi);
2098 devc->state = SIGMA_IDLE;
2099 sr_dev_acquisition_stop(sdi);
2106 * Periodically check the Sigma status when in CAPTURE mode. This routine
2107 * checks whether the configured sample count or sample time have passed,
2108 * and will stop acquisition and download the acquired samples.
2110 static int sigma_capture_mode(struct sr_dev_inst *sdi)
2112 struct dev_context *devc;
2114 uint32_t stoppos, triggerpos;
2116 gboolean full, wrapped, triggered, complete;
2121 * Get and interpret current acquisition status. Some of these
2122 * thresholds are rather arbitrary.
2124 ret = sigma_read_pos(devc, &stoppos, &triggerpos, &mode);
2127 stoppos >>= ROW_SHIFT;
2128 full = stoppos >= ROW_COUNT - 2;
2129 wrapped = mode & RMR_ROUND;
2130 triggered = mode & RMR_TRIGGERED;
2131 complete = mode & RMR_POSTTRIGGERED;
2134 * Acquisition completed in the hardware? Start or continue
2135 * sample memory content download.
2136 * (Can user initiated button presses result in auto stop?
2137 * Will they "trigger", and later result in expired time limit
2138 * of post trigger conditions?)
2141 return download_capture(sdi);
2144 * Previously configured acquisition period exceeded? Start
2145 * sample download. Start the timeout period late when triggers
2146 * are used (unknown period from acquisition start to trigger
2149 if (sr_sw_limits_check(&devc->limit.acquire))
2150 return download_capture(sdi);
2151 if (devc->late_trigger_timeout && triggered) {
2152 sr_sw_limits_acquisition_start(&devc->limit.acquire);
2153 devc->late_trigger_timeout = FALSE;
2157 * No trigger specified, and sample memory exhausted? Start
2158 * download (may otherwise keep acquiring, even for infinite
2159 * amounts of time without a user specified time/count limit).
2160 * This handles situations when users specify limits which
2161 * exceed the device's capabilities.
2164 if (!devc->use_triggers && wrapped)
2165 return download_capture(sdi);
2170 SR_PRIV int sigma_receive_data(int fd, int revents, void *cb_data)
2172 struct sr_dev_inst *sdi;
2173 struct dev_context *devc;
2181 if (devc->state == SIGMA_IDLE)
2185 * When the application has requested to stop the acquisition,
2186 * then immediately start downloading sample data. Continue a
2187 * previously initiated download until completion. Otherwise
2188 * keep checking configured limits which will terminate the
2189 * acquisition and initiate download.
2191 if (devc->state == SIGMA_STOPPING)
2192 return download_capture(sdi);
2193 if (devc->state == SIGMA_DOWNLOAD)
2194 return download_capture(sdi);
2195 if (devc->state == SIGMA_CAPTURE)
2196 return sigma_capture_mode(sdi);
2201 /* Build a LUT entry used by the trigger functions. */
2202 static void build_lut_entry(uint16_t *lut_entry,
2203 uint16_t spec_value, uint16_t spec_mask)
2205 size_t quad, bitidx, ch;
2206 uint16_t quadmask, bitmask;
2207 gboolean spec_value_low, bit_idx_low;
2210 * For each quad-channel-group, for each bit in the LUT (each
2211 * bit pattern of the channel signals, aka LUT address), for
2212 * each channel in the quad, setup the bit in the LUT entry.
2214 * Start from all-ones in the LUT (true, always matches), then
2215 * "pessimize the truthness" for specified conditions.
2217 for (quad = 0; quad < 4; quad++) {
2218 lut_entry[quad] = ~0;
2219 for (bitidx = 0; bitidx < 16; bitidx++) {
2220 for (ch = 0; ch < 4; ch++) {
2222 bitmask = quadmask << (quad * 4);
2223 if (!(spec_mask & bitmask))
2226 * This bit is part of the spec. The
2227 * condition which gets checked here
2228 * (got checked in all implementations
2229 * so far) is uncertain. A bit position
2230 * in the current index' number(!) is
2233 spec_value_low = !(spec_value & bitmask);
2234 bit_idx_low = !(bitidx & quadmask);
2235 if (spec_value_low == bit_idx_low)
2237 lut_entry[quad] &= ~BIT(bitidx);
2243 /* Add a logical function to LUT mask. */
2244 static void add_trigger_function(enum triggerop oper, enum triggerfunc func,
2245 size_t index, gboolean neg, uint16_t *mask)
2247 int x[2][2], a, b, aset, bset, rset;
2251 * Beware! The x, a, b, aset, bset, rset variables strictly
2252 * require the limited 0..1 range. They are not interpreted
2253 * as logically true, instead bit arith is done on them.
2256 /* Construct a pattern which detects the condition. */
2257 memset(x, 0, sizeof(x));
2287 case OP_NOTRISEFALL:
2293 /* Transpose the pattern if the condition is negated. */
2298 for (i = 0; i < 2; i++) {
2299 for (j = 0; j < 2; j++) {
2301 x[i][j] = x[1 - i][1 - j];
2302 x[1 - i][1 - j] = tmp;
2307 /* Update the LUT mask with the function's condition. */
2308 for (bitidx = 0; bitidx < 16; bitidx++) {
2309 a = (bitidx & BIT(2 * index + 0)) ? 1 : 0;
2310 b = (bitidx & BIT(2 * index + 1)) ? 1 : 0;
2312 aset = (*mask & BIT(bitidx)) ? 1 : 0;
2315 if (func == FUNC_AND || func == FUNC_NAND)
2317 else if (func == FUNC_OR || func == FUNC_NOR)
2319 else if (func == FUNC_XOR || func == FUNC_NXOR)
2324 if (func == FUNC_NAND || func == FUNC_NOR || func == FUNC_NXOR)
2328 *mask |= BIT(bitidx);
2330 *mask &= ~BIT(bitidx);
2335 * Build trigger LUTs used by 50 MHz and lower sample rates for supporting
2336 * simple pin change and state triggers. Only two transitions (rise/fall) can be
2337 * set at any time, but a full mask and value can be set (0/1).
2339 SR_PRIV int sigma_build_basic_trigger(struct dev_context *devc,
2340 struct triggerlut *lut)
2343 size_t bitidx, condidx;
2344 uint16_t value, mask;
2346 /* Setup something that "won't match" in the absence of a spec. */
2347 memset(lut, 0, sizeof(*lut));
2348 if (!devc->use_triggers)
2351 /* Start assuming simple triggers. Edges are handled below. */
2355 /* Process value/mask triggers. */
2356 value = devc->trigger.simplevalue;
2357 mask = devc->trigger.simplemask;
2358 build_lut_entry(lut->m2d, value, mask);
2360 /* Scan for and process rise/fall triggers. */
2361 memset(&masks, 0, sizeof(masks));
2363 for (bitidx = 0; bitidx < 16; bitidx++) {
2365 value = devc->trigger.risingmask | devc->trigger.fallingmask;
2366 if (!(value & mask))
2369 build_lut_entry(lut->m0d, mask, mask);
2371 build_lut_entry(lut->m1d, mask, mask);
2372 masks[condidx++] = mask;
2373 if (condidx == ARRAY_SIZE(masks))
2377 /* Add glue logic for rise/fall triggers. */
2378 if (masks[0] || masks[1]) {
2380 if (masks[0] & devc->trigger.risingmask)
2381 add_trigger_function(OP_RISE, FUNC_OR, 0, 0, &lut->m3q);
2382 if (masks[0] & devc->trigger.fallingmask)
2383 add_trigger_function(OP_FALL, FUNC_OR, 0, 0, &lut->m3q);
2384 if (masks[1] & devc->trigger.risingmask)
2385 add_trigger_function(OP_RISE, FUNC_OR, 1, 0, &lut->m3q);
2386 if (masks[1] & devc->trigger.fallingmask)
2387 add_trigger_function(OP_FALL, FUNC_OR, 1, 0, &lut->m3q);
2390 /* Triggertype: event. */
2391 lut->params.selres = TRGSEL_SELCODE_NEVER;
2392 lut->params.selinc = TRGSEL_SELCODE_LEVEL;
2393 lut->params.sela = 0; /* Counter >= CMPA && LEVEL */
2394 lut->params.cmpa = 0; /* Count 0 -> 1 already triggers. */