2 * This file is part of the libsigrok project.
4 * Copyright (C) 2010-2012 Håvard Espeland <gus@ping.uio.no>,
5 * Copyright (C) 2010 Martin Stensgård <mastensg@ping.uio.no>
6 * Copyright (C) 2010 Carl Henrik Lunde <chlunde@ping.uio.no>
8 * This program is free software: you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation, either version 3 of the License, or
11 * (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program. If not, see <http://www.gnu.org/licenses/>.
23 * ASIX SIGMA/SIGMA2 logic analyzer driver
30 * The ASIX Sigma supports arbitrary integer frequency divider in
31 * the 50MHz mode. The divider is in range 1...256 , allowing for
32 * very precise sampling rate selection. This driver supports only
33 * a subset of the sampling rates.
35 SR_PRIV const uint64_t samplerates[] = {
36 SR_KHZ(200), /* div=250 */
37 SR_KHZ(250), /* div=200 */
38 SR_KHZ(500), /* div=100 */
39 SR_MHZ(1), /* div=50 */
40 SR_MHZ(5), /* div=10 */
41 SR_MHZ(10), /* div=5 */
42 SR_MHZ(25), /* div=2 */
43 SR_MHZ(50), /* div=1 */
44 SR_MHZ(100), /* Special FW needed */
45 SR_MHZ(200), /* Special FW needed */
48 SR_PRIV const size_t samplerates_count = ARRAY_SIZE(samplerates);
50 static const char sigma_firmware_files[][24] = {
51 /* 50 MHz, supports 8 bit fractions */
57 /* Synchronous clock from pin */
58 "asix-sigma-50sync.fw",
59 /* Frequency counter */
60 "asix-sigma-phasor.fw",
63 static int sigma_read(void *buf, size_t size, struct dev_context *devc)
67 ret = ftdi_read_data(&devc->ftdic, (unsigned char *)buf, size);
69 sr_err("ftdi_read_data failed: %s",
70 ftdi_get_error_string(&devc->ftdic));
76 static int sigma_write(void *buf, size_t size, struct dev_context *devc)
80 ret = ftdi_write_data(&devc->ftdic, (unsigned char *)buf, size);
82 sr_err("ftdi_write_data failed: %s",
83 ftdi_get_error_string(&devc->ftdic));
84 } else if ((size_t) ret != size) {
85 sr_err("ftdi_write_data did not complete write.");
92 * NOTE: We chose the buffer size to be large enough to hold any write to the
93 * device. We still print a message just in case.
95 SR_PRIV int sigma_write_register(uint8_t reg, uint8_t *data, size_t len,
96 struct dev_context *devc)
102 if ((2 * len + 2) > sizeof(buf)) {
103 sr_err("Attempted to write %zu bytes, but buffer is too small.",
108 buf[idx++] = REG_ADDR_LOW | (reg & 0xf);
109 buf[idx++] = REG_ADDR_HIGH | (reg >> 4);
111 for (i = 0; i < len; i++) {
112 buf[idx++] = REG_DATA_LOW | (data[i] & 0xf);
113 buf[idx++] = REG_DATA_HIGH_WRITE | (data[i] >> 4);
116 return sigma_write(buf, idx, devc);
119 SR_PRIV int sigma_set_register(uint8_t reg, uint8_t value, struct dev_context *devc)
121 return sigma_write_register(reg, &value, 1, devc);
124 static int sigma_read_register(uint8_t reg, uint8_t *data, size_t len,
125 struct dev_context *devc)
129 buf[0] = REG_ADDR_LOW | (reg & 0xf);
130 buf[1] = REG_ADDR_HIGH | (reg >> 4);
131 buf[2] = REG_READ_ADDR;
133 sigma_write(buf, sizeof(buf), devc);
135 return sigma_read(data, len, devc);
138 static uint8_t sigma_get_register(uint8_t reg, struct dev_context *devc)
142 if (1 != sigma_read_register(reg, &value, 1, devc)) {
143 sr_err("sigma_get_register: 1 byte expected");
150 static int sigma_read_pos(uint32_t *stoppos, uint32_t *triggerpos,
151 struct dev_context *devc)
154 REG_ADDR_LOW | READ_TRIGGER_POS_LOW,
156 REG_READ_ADDR | NEXT_REG,
157 REG_READ_ADDR | NEXT_REG,
158 REG_READ_ADDR | NEXT_REG,
159 REG_READ_ADDR | NEXT_REG,
160 REG_READ_ADDR | NEXT_REG,
161 REG_READ_ADDR | NEXT_REG,
165 sigma_write(buf, sizeof(buf), devc);
167 sigma_read(result, sizeof(result), devc);
169 *triggerpos = result[0] | (result[1] << 8) | (result[2] << 16);
170 *stoppos = result[3] | (result[4] << 8) | (result[5] << 16);
172 /* Not really sure why this must be done, but according to spec. */
173 if ((--*stoppos & 0x1ff) == 0x1ff)
176 if ((*--triggerpos & 0x1ff) == 0x1ff)
182 static int sigma_read_dram(uint16_t startchunk, size_t numchunks,
183 uint8_t *data, struct dev_context *devc)
189 /* Send the startchunk. Index start with 1. */
191 buf[idx++] = startchunk >> 8;
192 buf[idx++] = startchunk & 0xff;
193 sigma_write_register(WRITE_MEMROW, buf, idx, devc);
197 buf[idx++] = REG_DRAM_BLOCK;
198 buf[idx++] = REG_DRAM_WAIT_ACK;
200 for (i = 0; i < numchunks; i++) {
201 /* Alternate bit to copy from DRAM to cache. */
202 if (i != (numchunks - 1))
203 buf[idx++] = REG_DRAM_BLOCK | (((i + 1) % 2) << 4);
205 buf[idx++] = REG_DRAM_BLOCK_DATA | ((i % 2) << 4);
207 if (i != (numchunks - 1))
208 buf[idx++] = REG_DRAM_WAIT_ACK;
211 sigma_write(buf, idx, devc);
213 return sigma_read(data, numchunks * CHUNK_SIZE, devc);
216 /* Upload trigger look-up tables to Sigma. */
217 SR_PRIV int sigma_write_trigger_lut(struct triggerlut *lut, struct dev_context *devc)
223 /* Transpose the table and send to Sigma. */
224 for (i = 0; i < 16; i++) {
229 if (lut->m2d[0] & bit)
231 if (lut->m2d[1] & bit)
233 if (lut->m2d[2] & bit)
235 if (lut->m2d[3] & bit)
245 if (lut->m0d[0] & bit)
247 if (lut->m0d[1] & bit)
249 if (lut->m0d[2] & bit)
251 if (lut->m0d[3] & bit)
254 if (lut->m1d[0] & bit)
256 if (lut->m1d[1] & bit)
258 if (lut->m1d[2] & bit)
260 if (lut->m1d[3] & bit)
263 sigma_write_register(WRITE_TRIGGER_SELECT0, tmp, sizeof(tmp),
265 sigma_set_register(WRITE_TRIGGER_SELECT1, 0x30 | i, devc);
268 /* Send the parameters */
269 sigma_write_register(WRITE_TRIGGER_SELECT0, (uint8_t *) &lut->params,
270 sizeof(lut->params), devc);
275 SR_PRIV void sigma_clear_helper(void *priv)
277 struct dev_context *devc;
281 ftdi_deinit(&devc->ftdic);
285 * Configure the FPGA for bitbang mode.
286 * This sequence is documented in section 2. of the ASIX Sigma programming
287 * manual. This sequence is necessary to configure the FPGA in the Sigma
288 * into Bitbang mode, in which it can be programmed with the firmware.
290 static int sigma_fpga_init_bitbang(struct dev_context *devc)
292 uint8_t suicide[] = {
293 0x84, 0x84, 0x88, 0x84, 0x88, 0x84, 0x88, 0x84,
295 uint8_t init_array[] = {
296 0x01, 0x03, 0x03, 0x01, 0x01, 0x01, 0x01, 0x01,
299 int i, ret, timeout = (10 * 1000);
302 /* Section 2. part 1), do the FPGA suicide. */
303 sigma_write(suicide, sizeof(suicide), devc);
304 sigma_write(suicide, sizeof(suicide), devc);
305 sigma_write(suicide, sizeof(suicide), devc);
306 sigma_write(suicide, sizeof(suicide), devc);
308 /* Section 2. part 2), do pulse on D1. */
309 sigma_write(init_array, sizeof(init_array), devc);
310 ftdi_usb_purge_buffers(&devc->ftdic);
312 /* Wait until the FPGA asserts D6/INIT_B. */
313 for (i = 0; i < timeout; i++) {
314 ret = sigma_read(&data, 1, devc);
317 /* Test if pin D6 got asserted. */
320 /* The D6 was not asserted yet, wait a bit. */
324 return SR_ERR_TIMEOUT;
328 * Configure the FPGA for logic-analyzer mode.
330 static int sigma_fpga_init_la(struct dev_context *devc)
332 /* Initialize the logic analyzer mode. */
333 uint8_t mode_regval = WMR_SDRAMINIT;
334 uint8_t logic_mode_start[] = {
335 REG_ADDR_LOW | (READ_ID & 0xf),
336 REG_ADDR_HIGH | (READ_ID >> 4),
337 REG_READ_ADDR, /* Read ID register. */
339 REG_ADDR_LOW | (WRITE_TEST & 0xf),
341 REG_DATA_HIGH_WRITE | 0x5,
342 REG_READ_ADDR, /* Read scratch register. */
345 REG_DATA_HIGH_WRITE | 0xa,
346 REG_READ_ADDR, /* Read scratch register. */
348 REG_ADDR_LOW | (WRITE_MODE & 0xf),
349 REG_DATA_LOW | (mode_regval & 0xf),
350 REG_DATA_HIGH_WRITE | (mode_regval >> 4),
356 /* Initialize the logic analyzer mode. */
357 sigma_write(logic_mode_start, sizeof(logic_mode_start), devc);
359 /* Expect a 3 byte reply since we issued three READ requests. */
360 ret = sigma_read(result, 3, devc);
364 if (result[0] != 0xa6 || result[1] != 0x55 || result[2] != 0xaa)
369 sr_err("Configuration failed. Invalid reply received.");
374 * Read the firmware from a file and transform it into a series of bitbang
375 * pulses used to program the FPGA. Note that the *bb_cmd must be free()'d
376 * by the caller of this function.
378 static int sigma_fw_2_bitbang(struct sr_context *ctx, const char *name,
379 uint8_t **bb_cmd, gsize *bb_cmd_size)
381 size_t i, file_size, bb_size;
383 uint8_t *bb_stream, *bbs;
388 /* Retrieve the on-disk firmware file content. */
389 firmware = sr_resource_load(ctx, SR_RESOURCE_FIRMWARE,
390 name, &file_size, 256 * 1024);
394 /* Unscramble the file content (XOR with "random" sequence). */
396 for (i = 0; i < file_size; i++) {
397 imm = (imm + 0xa853753) % 177 + (imm * 0x8034052);
398 firmware[i] ^= imm & 0xff;
402 * Generate a sequence of bitbang samples. With two samples per
403 * FPGA configuration bit, providing the level for the DIN signal
404 * as well as two edges for CCLK. See Xilinx UG332 for details
405 * ("slave serial" mode).
407 * Note that CCLK is inverted in hardware. That's why the
408 * respective bit is first set and then cleared in the bitbang
409 * sample sets. So that the DIN level will be stable when the
410 * data gets sampled at the rising CCLK edge, and the signals'
411 * setup time constraint will be met.
413 * The caller will put the FPGA into download mode, will send
414 * the bitbang samples, and release the allocated memory.
416 bb_size = file_size * 8 * 2;
417 bb_stream = (uint8_t *)g_try_malloc(bb_size);
419 sr_err("%s: Failed to allocate bitbang stream", __func__);
424 for (i = 0; i < file_size; i++) {
425 for (bit = 7; bit >= 0; bit--) {
426 v = (firmware[i] & (1 << bit)) ? 0x40 : 0x00;
432 /* The transformation completed successfully, return the result. */
434 *bb_cmd_size = bb_size;
441 static int upload_firmware(struct sr_context *ctx,
442 int firmware_idx, struct dev_context *devc)
448 const char *firmware;
449 struct ftdi_context *ftdic;
451 /* Avoid downloading the same firmware multiple times. */
452 firmware = sigma_firmware_files[firmware_idx];
453 if (devc->cur_firmware == firmware_idx) {
454 sr_info("Not uploading firmware file '%s' again.", firmware);
458 /* Make sure it's an ASIX SIGMA. */
459 ftdic = &devc->ftdic;
460 ret = ftdi_usb_open_desc(ftdic, USB_VENDOR, USB_PRODUCT,
461 USB_DESCRIPTION, NULL);
463 sr_err("ftdi_usb_open failed: %s",
464 ftdi_get_error_string(ftdic));
468 ret = ftdi_set_bitmode(ftdic, 0xdf, BITMODE_BITBANG);
470 sr_err("ftdi_set_bitmode failed: %s",
471 ftdi_get_error_string(ftdic));
475 /* Four times the speed of sigmalogan - Works well. */
476 ret = ftdi_set_baudrate(ftdic, 750 * 1000);
478 sr_err("ftdi_set_baudrate failed: %s",
479 ftdi_get_error_string(ftdic));
483 /* Initialize the FPGA for firmware upload. */
484 ret = sigma_fpga_init_bitbang(devc);
488 /* Prepare firmware. */
489 ret = sigma_fw_2_bitbang(ctx, firmware, &buf, &buf_size);
491 sr_err("An error occurred while reading the firmware: %s",
496 /* Upload firmware. */
497 sr_info("Uploading firmware file '%s'.", firmware);
498 sigma_write(buf, buf_size, devc);
502 ret = ftdi_set_bitmode(ftdic, 0x00, BITMODE_RESET);
504 sr_err("ftdi_set_bitmode failed: %s",
505 ftdi_get_error_string(ftdic));
509 ftdi_usb_purge_buffers(ftdic);
511 /* Discard garbage. */
512 while (sigma_read(&pins, 1, devc) == 1)
515 /* Initialize the FPGA for logic-analyzer mode. */
516 ret = sigma_fpga_init_la(devc);
520 devc->cur_firmware = firmware_idx;
522 sr_info("Firmware uploaded.");
528 * Sigma doesn't support limiting the number of samples, so we have to
529 * translate the number and the samplerate to an elapsed time.
531 * In addition we need to ensure that the last data cluster has passed
532 * the hardware pipeline, and became available to the PC side. With RLE
533 * compression up to 327ms could pass before another cluster accumulates
534 * at 200kHz samplerate when input pins don't change.
536 SR_PRIV uint64_t sigma_limit_samples_to_msec(const struct dev_context *devc,
537 uint64_t limit_samples)
540 uint64_t worst_cluster_time_ms;
542 limit_msec = limit_samples * 1000 / devc->cur_samplerate;
543 worst_cluster_time_ms = 65536 * 1000 / devc->cur_samplerate;
545 * One cluster time is not enough to flush pipeline when sampling
546 * grounded pins with 1 sample limit at 200kHz. Hence the 2* fix.
548 return limit_msec + 2 * worst_cluster_time_ms;
551 SR_PRIV int sigma_set_samplerate(const struct sr_dev_inst *sdi, uint64_t samplerate)
553 struct dev_context *devc;
554 struct drv_context *drvc;
559 drvc = sdi->driver->context;
562 /* Reject rates that are not in the list of supported rates. */
563 for (i = 0; i < samplerates_count; i++) {
564 if (samplerates[i] == samplerate)
567 if (i >= samplerates_count || samplerates[i] == 0)
568 return SR_ERR_SAMPLERATE;
571 * Depending on the samplerates of 200/100/50- MHz, specific
572 * firmware is required and higher rates might limit the set
573 * of available channels.
575 if (samplerate <= SR_MHZ(50)) {
576 ret = upload_firmware(drvc->sr_ctx, 0, devc);
577 devc->num_channels = 16;
578 } else if (samplerate == SR_MHZ(100)) {
579 ret = upload_firmware(drvc->sr_ctx, 1, devc);
580 devc->num_channels = 8;
581 } else if (samplerate == SR_MHZ(200)) {
582 ret = upload_firmware(drvc->sr_ctx, 2, devc);
583 devc->num_channels = 4;
587 * Derive the sample period from the sample rate as well as the
588 * number of samples that the device will communicate within
589 * an "event" (memory organization internal to the device).
592 devc->cur_samplerate = samplerate;
593 devc->samples_per_event = 16 / devc->num_channels;
594 devc->state.state = SIGMA_IDLE;
598 * Support for "limit_samples" is implemented by stopping
599 * acquisition after a corresponding period of time.
600 * Re-calculate that period of time, in case the limit is
601 * set first and the samplerate gets (re-)configured later.
603 if (ret == SR_OK && devc->limit_samples) {
605 msecs = sigma_limit_samples_to_msec(devc, devc->limit_samples);
606 devc->limit_msec = msecs;
613 * In 100 and 200 MHz mode, only a single pin rising/falling can be
614 * set as trigger. In other modes, two rising/falling triggers can be set,
615 * in addition to value/mask trigger for any number of channels.
617 * The Sigma supports complex triggers using boolean expressions, but this
618 * has not been implemented yet.
620 SR_PRIV int sigma_convert_trigger(const struct sr_dev_inst *sdi)
622 struct dev_context *devc;
623 struct sr_trigger *trigger;
624 struct sr_trigger_stage *stage;
625 struct sr_trigger_match *match;
627 int channelbit, trigger_set;
630 memset(&devc->trigger, 0, sizeof(struct sigma_trigger));
631 if (!(trigger = sr_session_trigger_get(sdi->session)))
635 for (l = trigger->stages; l; l = l->next) {
637 for (m = stage->matches; m; m = m->next) {
639 if (!match->channel->enabled)
640 /* Ignore disabled channels with a trigger. */
642 channelbit = 1 << (match->channel->index);
643 if (devc->cur_samplerate >= SR_MHZ(100)) {
644 /* Fast trigger support. */
646 sr_err("Only a single pin trigger is "
647 "supported in 100 and 200MHz mode.");
650 if (match->match == SR_TRIGGER_FALLING)
651 devc->trigger.fallingmask |= channelbit;
652 else if (match->match == SR_TRIGGER_RISING)
653 devc->trigger.risingmask |= channelbit;
655 sr_err("Only rising/falling trigger is "
656 "supported in 100 and 200MHz mode.");
662 /* Simple trigger support (event). */
663 if (match->match == SR_TRIGGER_ONE) {
664 devc->trigger.simplevalue |= channelbit;
665 devc->trigger.simplemask |= channelbit;
667 else if (match->match == SR_TRIGGER_ZERO) {
668 devc->trigger.simplevalue &= ~channelbit;
669 devc->trigger.simplemask |= channelbit;
671 else if (match->match == SR_TRIGGER_FALLING) {
672 devc->trigger.fallingmask |= channelbit;
675 else if (match->match == SR_TRIGGER_RISING) {
676 devc->trigger.risingmask |= channelbit;
681 * Actually, Sigma supports 2 rising/falling triggers,
682 * but they are ORed and the current trigger syntax
683 * does not permit ORed triggers.
685 if (trigger_set > 1) {
686 sr_err("Only 1 rising/falling trigger "
698 /* Software trigger to determine exact trigger position. */
699 static int get_trigger_offset(uint8_t *samples, uint16_t last_sample,
700 struct sigma_trigger *t)
705 for (i = 0; i < 8; i++) {
707 last_sample = sample;
708 sample = samples[2 * i] | (samples[2 * i + 1] << 8);
710 /* Simple triggers. */
711 if ((sample & t->simplemask) != t->simplevalue)
715 if (((last_sample & t->risingmask) != 0) ||
716 ((sample & t->risingmask) != t->risingmask))
720 if ((last_sample & t->fallingmask) != t->fallingmask ||
721 (sample & t->fallingmask) != 0)
727 /* If we did not match, return original trigger pos. */
732 * Return the timestamp of "DRAM cluster".
734 static uint16_t sigma_dram_cluster_ts(struct sigma_dram_cluster *cluster)
736 return (cluster->timestamp_hi << 8) | cluster->timestamp_lo;
740 * Return one 16bit data entity of a DRAM cluster at the specified index.
742 static uint16_t sigma_dram_cluster_data(struct sigma_dram_cluster *cl, int idx)
747 sample |= cl->samples[idx].sample_lo << 0;
748 sample |= cl->samples[idx].sample_hi << 8;
749 sample = (sample >> 8) | (sample << 8);
754 * Deinterlace sample data that was retrieved at 100MHz samplerate.
755 * One 16bit item contains two samples of 8bits each. The bits of
756 * multiple samples are interleaved.
758 static uint16_t sigma_deinterlace_100mhz_data(uint16_t indata, int idx)
764 outdata |= (indata >> (0 * 2 - 0)) & (1 << 0);
765 outdata |= (indata >> (1 * 2 - 1)) & (1 << 1);
766 outdata |= (indata >> (2 * 2 - 2)) & (1 << 2);
767 outdata |= (indata >> (3 * 2 - 3)) & (1 << 3);
768 outdata |= (indata >> (4 * 2 - 4)) & (1 << 4);
769 outdata |= (indata >> (5 * 2 - 5)) & (1 << 5);
770 outdata |= (indata >> (6 * 2 - 6)) & (1 << 6);
771 outdata |= (indata >> (7 * 2 - 7)) & (1 << 7);
776 * Deinterlace sample data that was retrieved at 200MHz samplerate.
777 * One 16bit item contains four samples of 4bits each. The bits of
778 * multiple samples are interleaved.
780 static uint16_t sigma_deinterlace_200mhz_data(uint16_t indata, int idx)
786 outdata |= (indata >> (0 * 4 - 0)) & (1 << 0);
787 outdata |= (indata >> (1 * 4 - 1)) & (1 << 1);
788 outdata |= (indata >> (2 * 4 - 2)) & (1 << 2);
789 outdata |= (indata >> (3 * 4 - 3)) & (1 << 3);
793 static void store_sr_sample(uint8_t *samples, int idx, uint16_t data)
795 samples[2 * idx + 0] = (data >> 0) & 0xff;
796 samples[2 * idx + 1] = (data >> 8) & 0xff;
800 * Local wrapper around sr_session_send() calls. Make sure to not send
801 * more samples to the session's datafeed than what was requested by a
802 * previously configured (optional) sample count.
804 static void sigma_session_send(struct sr_dev_inst *sdi,
805 struct sr_datafeed_packet *packet)
807 struct dev_context *devc;
808 struct sr_datafeed_logic *logic;
812 if (devc->limit_samples) {
813 logic = (void *)packet->payload;
814 send_now = logic->length / logic->unitsize;
815 if (devc->sent_samples + send_now > devc->limit_samples) {
816 send_now = devc->limit_samples - devc->sent_samples;
817 logic->length = send_now * logic->unitsize;
821 devc->sent_samples += send_now;
824 sr_session_send(sdi, packet);
828 * This size translates to: event count (1K events per cluster), times
829 * the sample width (unitsize, 16bits per event), times the maximum
830 * number of samples per event.
832 #define SAMPLES_BUFFER_SIZE (1024 * 2 * 4)
834 static void sigma_decode_dram_cluster(struct sigma_dram_cluster *dram_cluster,
835 unsigned int events_in_cluster,
836 unsigned int triggered,
837 struct sr_dev_inst *sdi)
839 struct dev_context *devc = sdi->priv;
840 struct sigma_state *ss = &devc->state;
841 struct sr_datafeed_packet packet;
842 struct sr_datafeed_logic logic;
843 uint16_t tsdiff, ts, sample, item16;
844 uint8_t samples[SAMPLES_BUFFER_SIZE];
846 size_t send_count, trig_count;
850 ts = sigma_dram_cluster_ts(dram_cluster);
851 tsdiff = ts - ss->lastts;
852 ss->lastts = ts + EVENTS_PER_CLUSTER;
854 packet.type = SR_DF_LOGIC;
855 packet.payload = &logic;
857 logic.data = samples;
860 * If this cluster is not adjacent to the previously received
861 * cluster, then send the appropriate number of samples with the
862 * previous values to the sigrok session. This "decodes RLE".
864 for (ts = 0; ts < tsdiff; ts++) {
866 store_sr_sample(samples, i, ss->lastsample);
869 * If we have 1024 samples ready or we're at the
870 * end of submitting the padding samples, submit
871 * the packet to Sigrok. Since constant data is
872 * sent, duplication of data for rates above 50MHz
875 if ((i == 1023) || (ts == tsdiff - 1)) {
876 logic.length = (i + 1) * logic.unitsize;
877 for (j = 0; j < devc->samples_per_event; j++)
878 sigma_session_send(sdi, &packet);
883 * Parse the samples in current cluster and prepare them
884 * to be submitted to Sigrok. Cope with memory layouts that
885 * vary with the samplerate.
887 send_ptr = &samples[0];
890 for (i = 0; i < events_in_cluster; i++) {
891 item16 = sigma_dram_cluster_data(dram_cluster, i);
892 if (devc->cur_samplerate == SR_MHZ(200)) {
893 sample = sigma_deinterlace_200mhz_data(item16, 0);
894 store_sr_sample(samples, send_count++, sample);
895 sample = sigma_deinterlace_200mhz_data(item16, 1);
896 store_sr_sample(samples, send_count++, sample);
897 sample = sigma_deinterlace_200mhz_data(item16, 2);
898 store_sr_sample(samples, send_count++, sample);
899 sample = sigma_deinterlace_200mhz_data(item16, 3);
900 store_sr_sample(samples, send_count++, sample);
901 } else if (devc->cur_samplerate == SR_MHZ(100)) {
902 sample = sigma_deinterlace_100mhz_data(item16, 0);
903 store_sr_sample(samples, send_count++, sample);
904 sample = sigma_deinterlace_100mhz_data(item16, 1);
905 store_sr_sample(samples, send_count++, sample);
908 store_sr_sample(samples, send_count++, sample);
913 * If a trigger position applies, then provide the datafeed with
914 * the first part of data up to that position, then send the
917 int trigger_offset = 0;
920 * Trigger is not always accurate to sample because of
921 * pipeline delay. However, it always triggers before
922 * the actual event. We therefore look at the next
923 * samples to pinpoint the exact position of the trigger.
925 trigger_offset = get_trigger_offset(samples,
926 ss->lastsample, &devc->trigger);
928 if (trigger_offset > 0) {
929 trig_count = trigger_offset * devc->samples_per_event;
930 packet.type = SR_DF_LOGIC;
931 logic.length = trig_count * logic.unitsize;
932 sigma_session_send(sdi, &packet);
933 send_ptr += trig_count * logic.unitsize;
934 send_count -= trig_count;
937 /* Only send trigger if explicitly enabled. */
938 if (devc->use_triggers) {
939 packet.type = SR_DF_TRIGGER;
940 sr_session_send(sdi, &packet);
945 * Send the data after the trigger, or all of the received data
946 * if no trigger position applies.
949 packet.type = SR_DF_LOGIC;
950 logic.length = send_count * logic.unitsize;
951 logic.data = send_ptr;
952 sigma_session_send(sdi, &packet);
955 ss->lastsample = sample;
959 * Decode chunk of 1024 bytes, 64 clusters, 7 events per cluster.
960 * Each event is 20ns apart, and can contain multiple samples.
962 * For 200 MHz, events contain 4 samples for each channel, spread 5 ns apart.
963 * For 100 MHz, events contain 2 samples for each channel, spread 10 ns apart.
964 * For 50 MHz and below, events contain one sample for each channel,
965 * spread 20 ns apart.
967 static int decode_chunk_ts(struct sigma_dram_line *dram_line,
968 uint16_t events_in_line,
969 uint32_t trigger_event,
970 struct sr_dev_inst *sdi)
972 struct sigma_dram_cluster *dram_cluster;
973 struct dev_context *devc;
974 unsigned int clusters_in_line;
975 unsigned int events_in_cluster;
977 uint32_t trigger_cluster, triggered;
980 clusters_in_line = events_in_line;
981 clusters_in_line += EVENTS_PER_CLUSTER - 1;
982 clusters_in_line /= EVENTS_PER_CLUSTER;
983 trigger_cluster = ~0;
986 /* Check if trigger is in this chunk. */
987 if (trigger_event < (64 * 7)) {
988 if (devc->cur_samplerate <= SR_MHZ(50)) {
989 trigger_event -= MIN(EVENTS_PER_CLUSTER - 1,
993 /* Find in which cluster the trigger occurred. */
994 trigger_cluster = trigger_event / EVENTS_PER_CLUSTER;
997 /* For each full DRAM cluster. */
998 for (i = 0; i < clusters_in_line; i++) {
999 dram_cluster = &dram_line->cluster[i];
1001 /* The last cluster might not be full. */
1002 if ((i == clusters_in_line - 1) &&
1003 (events_in_line % EVENTS_PER_CLUSTER)) {
1004 events_in_cluster = events_in_line % EVENTS_PER_CLUSTER;
1006 events_in_cluster = EVENTS_PER_CLUSTER;
1009 triggered = (i == trigger_cluster);
1010 sigma_decode_dram_cluster(dram_cluster, events_in_cluster,
1017 static int download_capture(struct sr_dev_inst *sdi)
1019 const uint32_t chunks_per_read = 32;
1021 struct dev_context *devc;
1022 struct sigma_dram_line *dram_line;
1024 uint32_t stoppos, triggerpos;
1027 uint32_t dl_lines_total, dl_lines_curr, dl_lines_done;
1028 uint32_t dl_first_line, dl_line;
1029 uint32_t dl_events_in_line;
1030 uint32_t trg_line, trg_event;
1033 dl_events_in_line = 64 * 7;
1037 dram_line = g_try_malloc0(chunks_per_read * sizeof(*dram_line));
1041 sr_info("Downloading sample data.");
1044 * Ask the hardware to stop data acquisition. Reception of the
1045 * FORCESTOP request makes the hardware "disable RLE" (store
1046 * clusters to DRAM regardless of whether pin state changes) and
1047 * raise the POSTTRIGGERED flag.
1049 sigma_set_register(WRITE_MODE, WMR_FORCESTOP | WMR_SDRAMWRITEEN, devc);
1051 modestatus = sigma_get_register(READ_MODE, devc);
1052 } while (!(modestatus & RMR_POSTTRIGGERED));
1054 /* Set SDRAM Read Enable. */
1055 sigma_set_register(WRITE_MODE, WMR_SDRAMREADEN, devc);
1057 /* Get the current position. */
1058 sigma_read_pos(&stoppos, &triggerpos, devc);
1060 /* Check if trigger has fired. */
1061 modestatus = sigma_get_register(READ_MODE, devc);
1062 if (modestatus & RMR_TRIGGERED) {
1063 trg_line = triggerpos >> 9;
1064 trg_event = triggerpos & 0x1ff;
1067 devc->sent_samples = 0;
1070 * Determine how many "DRAM lines" of 1024 bytes each we need to
1071 * retrieve from the Sigma hardware, so that we have a complete
1072 * set of samples. Note that the last line need not contain 64
1073 * clusters, it might be partially filled only.
1075 * When RMR_ROUND is set, the circular buffer in DRAM has wrapped
1076 * around. Since the status of the very next line is uncertain in
1077 * that case, we skip it and start reading from the next line. The
1078 * circular buffer has 32K lines (0x8000).
1080 dl_lines_total = (stoppos >> 9) + 1;
1081 if (modestatus & RMR_ROUND) {
1082 dl_first_line = dl_lines_total + 1;
1083 dl_lines_total = 0x8000 - 2;
1088 while (dl_lines_total > dl_lines_done) {
1089 /* We can download only up-to 32 DRAM lines in one go! */
1090 dl_lines_curr = MIN(chunks_per_read, dl_lines_total - dl_lines_done);
1092 dl_line = dl_first_line + dl_lines_done;
1094 bufsz = sigma_read_dram(dl_line, dl_lines_curr,
1095 (uint8_t *)dram_line, devc);
1096 /* TODO: Check bufsz. For now, just avoid compiler warnings. */
1099 /* This is the first DRAM line, so find the initial timestamp. */
1100 if (dl_lines_done == 0) {
1101 devc->state.lastts =
1102 sigma_dram_cluster_ts(&dram_line[0].cluster[0]);
1103 devc->state.lastsample = 0;
1106 for (i = 0; i < dl_lines_curr; i++) {
1107 uint32_t trigger_event = ~0;
1108 /* The last "DRAM line" can be only partially full. */
1109 if (dl_lines_done + i == dl_lines_total - 1)
1110 dl_events_in_line = stoppos & 0x1ff;
1112 /* Test if the trigger happened on this line. */
1113 if (dl_lines_done + i == trg_line)
1114 trigger_event = trg_event;
1116 decode_chunk_ts(dram_line + i, dl_events_in_line,
1117 trigger_event, sdi);
1120 dl_lines_done += dl_lines_curr;
1123 std_session_send_df_end(sdi);
1125 sdi->driver->dev_acquisition_stop(sdi);
1133 * Periodically check the Sigma status when in CAPTURE mode. This routine
1134 * checks whether the configured sample count or sample time have passed,
1135 * and will stop acquisition and download the acquired samples.
1137 static int sigma_capture_mode(struct sr_dev_inst *sdi)
1139 struct dev_context *devc;
1140 uint64_t running_msec;
1141 uint64_t current_time;
1146 * Check if the selected sampling duration passed. Sample count
1147 * limits are covered by this enforced timeout as well.
1149 current_time = g_get_monotonic_time();
1150 running_msec = (current_time - devc->start_time) / 1000;
1151 if (running_msec >= devc->limit_msec)
1152 return download_capture(sdi);
1157 SR_PRIV int sigma_receive_data(int fd, int revents, void *cb_data)
1159 struct sr_dev_inst *sdi;
1160 struct dev_context *devc;
1168 if (devc->state.state == SIGMA_IDLE)
1171 if (devc->state.state == SIGMA_CAPTURE)
1172 return sigma_capture_mode(sdi);
1177 /* Build a LUT entry used by the trigger functions. */
1178 static void build_lut_entry(uint16_t value, uint16_t mask, uint16_t *entry)
1182 /* For each quad channel. */
1183 for (i = 0; i < 4; i++) {
1186 /* For each bit in LUT. */
1187 for (j = 0; j < 16; j++)
1189 /* For each channel in quad. */
1190 for (k = 0; k < 4; k++) {
1191 bit = 1 << (i * 4 + k);
1193 /* Set bit in entry */
1194 if ((mask & bit) && ((!(value & bit)) !=
1196 entry[i] &= ~(1 << j);
1201 /* Add a logical function to LUT mask. */
1202 static void add_trigger_function(enum triggerop oper, enum triggerfunc func,
1203 int index, int neg, uint16_t *mask)
1206 int x[2][2], tmp, a, b, aset, bset, rset;
1208 memset(x, 0, 4 * sizeof(int));
1210 /* Trigger detect condition. */
1240 case OP_NOTRISEFALL:
1246 /* Transpose if neg is set. */
1248 for (i = 0; i < 2; i++) {
1249 for (j = 0; j < 2; j++) {
1251 x[i][j] = x[1 - i][1 - j];
1252 x[1 - i][1 - j] = tmp;
1257 /* Update mask with function. */
1258 for (i = 0; i < 16; i++) {
1259 a = (i >> (2 * index + 0)) & 1;
1260 b = (i >> (2 * index + 1)) & 1;
1262 aset = (*mask >> i) & 1;
1266 if (func == FUNC_AND || func == FUNC_NAND)
1268 else if (func == FUNC_OR || func == FUNC_NOR)
1270 else if (func == FUNC_XOR || func == FUNC_NXOR)
1273 if (func == FUNC_NAND || func == FUNC_NOR || func == FUNC_NXOR)
1284 * Build trigger LUTs used by 50 MHz and lower sample rates for supporting
1285 * simple pin change and state triggers. Only two transitions (rise/fall) can be
1286 * set at any time, but a full mask and value can be set (0/1).
1288 SR_PRIV int sigma_build_basic_trigger(struct triggerlut *lut, struct dev_context *devc)
1291 uint16_t masks[2] = { 0, 0 };
1293 memset(lut, 0, sizeof(struct triggerlut));
1295 /* Constant for simple triggers. */
1298 /* Value/mask trigger support. */
1299 build_lut_entry(devc->trigger.simplevalue, devc->trigger.simplemask,
1302 /* Rise/fall trigger support. */
1303 for (i = 0, j = 0; i < 16; i++) {
1304 if (devc->trigger.risingmask & (1 << i) ||
1305 devc->trigger.fallingmask & (1 << i))
1306 masks[j++] = 1 << i;
1309 build_lut_entry(masks[0], masks[0], lut->m0d);
1310 build_lut_entry(masks[1], masks[1], lut->m1d);
1312 /* Add glue logic */
1313 if (masks[0] || masks[1]) {
1314 /* Transition trigger. */
1315 if (masks[0] & devc->trigger.risingmask)
1316 add_trigger_function(OP_RISE, FUNC_OR, 0, 0, &lut->m3);
1317 if (masks[0] & devc->trigger.fallingmask)
1318 add_trigger_function(OP_FALL, FUNC_OR, 0, 0, &lut->m3);
1319 if (masks[1] & devc->trigger.risingmask)
1320 add_trigger_function(OP_RISE, FUNC_OR, 1, 0, &lut->m3);
1321 if (masks[1] & devc->trigger.fallingmask)
1322 add_trigger_function(OP_FALL, FUNC_OR, 1, 0, &lut->m3);
1324 /* Only value/mask trigger. */
1328 /* Triggertype: event. */
1329 lut->params.selres = 3;