2 * This file is part of the libsigrok project.
4 * Copyright (C) 2010 Håvard Espeland <gus@ping.uio.no>,
5 * Copyright (C) 2010 Martin Stensgård <mastensg@ping.uio.no>
6 * Copyright (C) 2010 Carl Henrik Lunde <chlunde@ping.uio.no>
8 * This program is free software: you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation, either version 3 of the License, or
11 * (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program. If not, see <http://www.gnu.org/licenses/>.
22 #ifndef LIBSIGROK_HARDWARE_ASIX_SIGMA_ASIX_SIGMA_H
23 #define LIBSIGROK_HARDWARE_ASIX_SIGMA_ASIX_SIGMA_H
25 #define LOG_PREFIX "asix-sigma"
27 enum sigma_write_register {
28 WRITE_CLOCK_SELECT = 0,
29 WRITE_TRIGGER_SELECT0 = 1,
30 WRITE_TRIGGER_SELECT1 = 2,
33 WRITE_POST_TRIGGER = 5,
34 WRITE_TRIGGER_OPTION = 6,
40 enum sigma_read_register {
42 READ_TRIGGER_POS_LOW = 1,
43 READ_TRIGGER_POS_HIGH = 2,
44 READ_TRIGGER_POS_UP = 3,
45 READ_STOP_POS_LOW = 4,
46 READ_STOP_POS_HIGH = 5,
49 READ_PIN_CHANGE_LOW = 8,
50 READ_PIN_CHANGE_HIGH = 9,
51 READ_BLOCK_LAST_TS_LOW = 10,
52 READ_BLOCK_LAST_TS_HIGH = 11,
58 #define REG_ADDR_LOW (0x0 << 4)
59 #define REG_ADDR_HIGH (0x1 << 4)
60 #define REG_DATA_LOW (0x2 << 4)
61 #define REG_DATA_HIGH_WRITE (0x3 << 4)
62 #define REG_READ_ADDR (0x4 << 4)
63 #define REG_DRAM_WAIT_ACK (0x5 << 4)
65 /* Bit (1 << 4) can be low or high (double buffer / cache) */
66 #define REG_DRAM_BLOCK (0x6 << 4)
67 #define REG_DRAM_BLOCK_BEGIN (0x8 << 4)
68 #define REG_DRAM_BLOCK_DATA (0xa << 4)
75 #define EVENTS_PER_CLUSTER 7
77 #define CHUNK_SIZE 1024
80 * The entire ASIX Sigma DRAM is an array of struct sigma_dram_line[1024];
83 /* One "DRAM cluster" contains a timestamp and 7 samples, 16b total. */
84 struct sigma_dram_cluster {
93 /* One "DRAM line" contains 64 "DRAM clusters", 1024b total. */
94 struct sigma_dram_line {
95 struct sigma_dram_cluster cluster[64];
98 struct clockselect_50 {
101 uint16_t disabled_channels;
104 /* The effect of all these are still a bit unclear. */
105 struct triggerinout {
106 uint8_t trgout_resistor_enable : 1;
107 uint8_t trgout_resistor_pullup : 1;
108 uint8_t reserved1 : 1;
109 uint8_t trgout_bytrigger : 1;
110 uint8_t trgout_byevent : 1;
111 uint8_t trgout_bytriggerin : 1;
112 uint8_t reserved2 : 2;
114 /* Should be set same as the first two */
115 uint8_t trgout_resistor_enable2 : 1;
116 uint8_t trgout_resistor_pullup2 : 1;
118 uint8_t reserved3 : 1;
119 uint8_t trgout_long : 1;
120 uint8_t trgout_pin : 1; /* Use 1k resistor. Pullup? */
121 uint8_t trgin_negate : 1;
122 uint8_t trgout_enable : 1;
123 uint8_t trgin_enable : 1;
127 /* The actual LUTs. */
128 uint16_t m0d[4], m1d[4], m2d[4];
129 uint16_t m3, m3s, m4;
131 /* Paramters should be sent as a single register write. */
134 uint8_t selpresc : 6;
146 /* Trigger configuration */
147 struct sigma_trigger {
148 /* Only two channels can be used in mask. */
150 uint16_t fallingmask;
152 /* Simple trigger support (<= 50 MHz). */
154 uint16_t simplevalue;
156 /* TODO: Advanced trigger support (boolean expressions). */
159 /* Events for trigger operation. */
171 /* Logical functions for trigger operation. */
183 SIGMA_UNINITIALIZED = 0,
193 /* Private, per-device-instance driver context. */
195 struct ftdi_context ftdic;
196 uint64_t cur_samplerate;
199 struct timeval start_tv;
203 int samples_per_event;
205 struct sigma_trigger trigger;
207 struct sigma_state state;